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docs/verilog_frontend.rst: Fix indentation

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Krystine Sherwin 2025-06-25 10:39:50 +12:00 • committed by Emil J. Tywoniak
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commit b90622b7ed
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docs/source/yosys_internals/flow/verilog_frontend.rst
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@ -187,13 +187,13 @@ simplifies the creation of AST nodes for simple expressions a bit. For example
the bison code for parsing multiplications: the bison code for parsing multiplications:
.. code:: none .. code:: none
:number-lines: :number-lines:
basic_expr TOK_ASTER attr basic_expr { basic_expr TOK_ASTER attr basic_expr {
$$ = std::make_unique<AstNode>(AST_MUL, std::move($1), std::move($4)); $$ = std::make_unique<AstNode>(AST_MUL, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4); SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3); append_attr($$.get(), $3);
} | } |
The generated AST data structure is then passed directly to the AST frontend The generated AST data structure is then passed directly to the AST frontend
that performs the actual conversion to RTLIL. that performs the actual conversion to RTLIL.