mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-20 11:22:05 +00:00
Code Activity

docs/verilog_frontend.rst: Fix indentation

Browse source
This commit is contained in:
Krystine Sherwin 2025-06-25 10:39:50 +12:00 • committed by Emil J. Tywoniak
parent 7b5035e0c4
commit b90622b7ed
1 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

12
docs/source/yosys_internals/flow/verilog_frontend.rst
View file

@ -187,13 +187,13 @@ simplifies the creation of AST nodes for simple expressions a bit. For example
the bison code for parsing multiplications:
.. code:: none
:number-lines:
:number-lines:
basic_expr TOK_ASTER attr basic_expr {
$$ = std::make_unique<AstNode>(AST_MUL, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
} |
basic_expr TOK_ASTER attr basic_expr {
$$ = std::make_unique<AstNode>(AST_MUL, std::move($1), std::move($4));
SET_AST_NODE_LOC($$.get(), @1, @4);
append_attr($$.get(), $3);
} |
The generated AST data structure is then passed directly to the AST frontend
that performs the actual conversion to RTLIL.