mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-08 23:23:25 +00:00
Code Activity

Merge 10bb0f472f into 0fcf5c080d

Browse source
This commit is contained in:
garytwong 2025-06-04 14:06:34 +00:00 • committed by GitHub
commit b8ed809d26
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
6 changed files with 204 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

8
docs/source/yosys_internals/verilog.rst
View file

@ -377,7 +377,7 @@ from SystemVerilog:
- Assignments within expressions are supported.
- The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are
accepted on ``if`` and ``case`` conditionals. (Those keywords are currently
handled in the same way as their equivalent ``full_case`` and
``parallel_case`` attributes on ``case`` statements, and checked
for syntactic validity but otherwise ignored on ``if`` statements.)
supported on ``if`` and ``case`` conditionals. (The Verilog frontend
will process conditionals using these keywords by annotating their
representation with the appropriate ``full_case`` and/or ``parallel_case``
attributes, which are described above.)