mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-16 06:31:29 +00:00
Code Activity

DSP48E1 sim model: add SIMD tests

Browse source 
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-08-08 11:39:35 +01:00
parent 57aeb4cc01
commit b8cd4ad64a
3 changed files with 113 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/xilinx/tests/test_dsp_model.sh
View file

@ -4,8 +4,10 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v >
if [ ! -f "test_dsp_model_ref.v" ]; then
cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
fi
for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \
mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc
for tb in simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \
mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \
mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc \
do
iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
vvp -N ./test_dsp_model