mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-04 10:20:24 +00:00
Code Activity

One more and tidy up

Browse source
This commit is contained in:
Eddie Hung 2019-06-06 12:03:44 -07:00
parent 5d4eca5a29
commit b8620f7b3d
2 changed files with 29 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

20
tests/various/muxpack.v
View file

@ -5,7 +5,6 @@ always @*
else if (s == 2) o <= i[2*W+:W];
else if (s == 3) o <= i[3*W+:W];
else o <= {W{1'bx}};
endmodule
module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@ -17,7 +16,6 @@ always @* begin
if (s == 3) o <= i[3*W+:W];
if (s == 4) o <= i[4*W+:W];
end
endmodule
module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@ -32,7 +30,6 @@ always @*
else o <= i[2*W+:W];
else o <= i[1*W+:W];
else o <= {W{1'bx}};
endmodule
module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
@ -44,10 +41,9 @@ always @* begin
if (s == 3) o <= i[3*W+:W];
if (s == 4) o <= i[4*W+:W];
end
endmodule
module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
if (s == 0) o <= i[0*W+:W];
// else if (s == 1) o <= i[1*W+:W];
@ -55,5 +51,17 @@ always @* begin
else if (s == 3) o <= i[3*W+:W];
else o <= {W{1'bx}};
end
endmodule
module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {W{1'bx}};
if (s == 3) o <= i[3*W+:W];
if (s == 2) o <= i[2*W+:W];
if (s == 1) o <= i[1*W+:W];
if (s == 4) o <= i[4*W+:W];
if (s == 0) o <= i[0*W+:W];
end
endmodule