mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-14 06:45:26 +00:00
Code Activity

fixup! box_derive: add -apply

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-06-25 14:14:31 +02:00
parent 424f9f91aa
commit b85bd37360
2 changed files with 18 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

11
passes/cmds/box_derive.cc
View file

@ -86,7 +86,6 @@ struct BoxDerivePass : Pass {
for (auto module : d->selected_modules()) {
for (auto cell : module->selected_cells()) {
log_cell(cell);
Module *inst_module = d->module(cell->type);
if (!inst_module || !inst_module->get_blackbox_attribute())
continue;
@ -97,13 +96,14 @@ struct BoxDerivePass : Pass {
auto index = std::make_pair(base->name, cell->parameters);
if (cell->parameters.empty() || done.count(index))
if (cell->parameters.empty())
continue;
if (!done.count(index)) {
IdString derived_type = base->derive(d, cell->parameters);
Module *derived = d->module(derived_type);
log_assert(derived && "Failed to derive module\n");
log_debug("derived %s\n", derived_type.c_str());
log("derived %s\n", derived_type.c_str());
if (!naming_attr.empty() && derived->has_attribute(naming_attr)) {
IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));
@ -115,9 +115,10 @@ struct BoxDerivePass : Pass {
}
done[index] = derived;
}
if (apply_mode)
cell->type = derived_type;
log_cell(cell);
cell->type = done[index]->name;
}
}
}

2
passes/cmds/publish.cc
View file

@ -22,7 +22,7 @@ public:
log("\n");
log(" publish\n");
log("Makes all module names and cell types public by prefixing\n");
log("% with \\.\n");
log("%% with \\.\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{