mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

fix stuff, don't strip

Browse source
This commit is contained in:
Emil J. Tywoniak 2024-06-05 22:21:31 +02:00
parent 60bf00ea79
commit b85062fcec
2 changed files with 2 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

3
flake.nix
View file

@ -24,12 +24,13 @@
preConfigure = "make config-clang"; preConfigure = "make config-clang";
checkTarget = "test"; checkTarget = "test";
installPhase = '' installPhase = ''
make install PREFIX=$out ABCEXTERNAL=yosys-abc make install PREFIX=$out ABCEXTERNAL=yosys-abc STRIP=\#
ln -s ${abc-verifier}/bin/abc $out/bin/yosys-abc ln -s ${abc-verifier}/bin/abc $out/bin/yosys-abc
''; '';
buildPhase = '' buildPhase = ''
make -j$(nproc) ABCEXTERNAL=yosys-abc make -j$(nproc) ABCEXTERNAL=yosys-abc
''; '';
dontStrip = true;
meta = with pkgs.lib; { meta = with pkgs.lib; {
description = "Yosys Open SYnthesis Suite"; description = "Yosys Open SYnthesis Suite";
homepage = "https://yosyshq.net/yosys/"; homepage = "https://yosyshq.net/yosys/";

8
kernel/rtlil.cc
View file

@ -928,7 +928,6 @@ RTLIL::Module::Module()
design = nullptr; design = nullptr;
refcount_wires_ = 0; refcount_wires_ = 0;
refcount_cells_ = 0; refcount_cells_ = 0;
TracyAllocN(this, sizeof(RTLIL::Module), "module");
#ifdef WITH_PYTHON #ifdef WITH_PYTHON
RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this)); RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
@ -947,7 +946,6 @@ RTLIL::Module::~Module()
delete pr.second; delete pr.second;
for (auto binding : bindings_) for (auto binding : bindings_)
delete binding; delete binding;
TracyFree(this);
#ifdef WITH_PYTHON #ifdef WITH_PYTHON
RTLIL::Module::get_all_modules()->erase(hashidx_); RTLIL::Module::get_all_modules()->erase(hashidx_);
#endif #endif
@ -3460,17 +3458,11 @@ RTLIL::Memory::Memory()
#endif #endif
} }
RTLIL::Process::~Process()
{
TracyFree(this);
}
RTLIL::Process::Process() : module(nullptr) RTLIL::Process::Process() : module(nullptr)
{ {
static unsigned int hashidx_count = 123456789; static unsigned int hashidx_count = 123456789;
hashidx_count = mkhash_xorshift(hashidx_count); hashidx_count = mkhash_xorshift(hashidx_count);
hashidx_ = hashidx_count; hashidx_ = hashidx_count;
TracyAllocN(this, sizeof(RTLIL::Process), "process");
} }
RTLIL::Cell::Cell() : module(nullptr) RTLIL::Cell::Cell() : module(nullptr)