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Added $macc cell type

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This commit is contained in:
Clifford Wolf 2014-09-06 15:47:46 +02:00
parent 76f8128123
commit b847ec8a0b
4 changed files with 242 additions and 9 deletions
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14
kernel/rtlil.cc
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@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
#include "kernel/macc.h"
#include "frontends/verilog/verilog_frontend.h"
#include "backends/ilang/ilang_backend.h"
@ -633,6 +634,17 @@ namespace {
return;
}
if (cell->type == "$macc") {
param("\\CONFIG");
param("\\CONFIG_WIDTH");
port("\\A", param("\\A_WIDTH"));
port("\\B", param("\\B_WIDTH"));
port("\\Y", param("\\Y_WIDTH"));
check_expected();
Macc().from_cell(cell);
return;
}
if (cell->type == "$logic_not") {
param_bool("\\A_SIGNED");
port("\\A", param("\\A_WIDTH"));
@ -1781,7 +1793,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
return;
}
bool signedness_ab = !type.in("$slice", "$concat");
bool signedness_ab = !type.in("$slice", "$concat", "$macc");
if (connections_.count("\\A")) {
if (signedness_ab) {