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Comment to explain separating CREG packing

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This commit is contained in:
Eddie Hung 2019-09-23 13:58:10 -07:00
parent 15dfbc8125
commit b824a56cde
1 changed files with 8 additions and 0 deletions
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8
passes/pmgen/xilinx_dsp.cc
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@ -606,6 +606,14 @@ struct XilinxDspPass : public Pass {
xilinx_dsp_pm pm(module, module->selected_cells()); xilinx_dsp_pm pm(module, module->selected_cells());
pm.run_xilinx_dsp_pack(xilinx_dsp_pack); pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
} }
// Separating out CREG packing is necessary since there
// is no guarantee that the cell ordering corresponds
// to the "expected" case (i.e. the order in which
// they appear in the source) thus the possiblity
// existed that a register got packed as CREG into a
// downstream DSP that should have otherwise been a
// PREG of an upstream DSP that had not been pattern
// matched yet
{ {
xilinx_dsp_CREG_pm pm(module, module->selected_cells()); xilinx_dsp_CREG_pm pm(module, module->selected_cells());
pm.run_xilinx_dsp_packC(xilinx_dsp_packC); pm.run_xilinx_dsp_packC(xilinx_dsp_packC);