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Add test case from #997

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2019-05-07 19:58:04 +02:00
parent 33738c1745
commit b7ec698d40
1 changed files with 12 additions and 0 deletions
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12
tests/simple/dff_init.v
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@ -40,3 +40,15 @@ module dff1a_test(n1, n1_inv, clk);
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
module dff_test_997 (y, clk, wire4);
// https://github.com/YosysHQ/yosys/issues/997
output wire [1:0] y;
input clk;
input signed wire4;
reg [1:0] reg10 = 0;
always @(posedge clk) begin
reg10 <= wire4;
end
assign y = reg10;
endmodule