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Changed users of cell->connections_ to the new API (sed command)

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git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
This commit is contained in:
Clifford Wolf 2014-07-26 14:32:50 +02:00
parent cd6574ecf6
commit b7dda72302
61 changed files with 1201 additions and 1201 deletions
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14
passes/sat/freduce.cc
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@ -610,7 +610,7 @@ struct FreduceWorker
for (auto &it : module->cells) {
if (ct.cell_known(it.second->type)) {
std::set<RTLIL::SigBit> inputs, outputs;
for (auto &port : it.second->connections_) {
for (auto &port : it.second->connections()) {
std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
if (ct.cell_output(it.second->type, port.first))
outputs.insert(bits.begin(), bits.end());
@ -624,7 +624,7 @@ struct FreduceWorker
bits_full_total += outputs.size();
}
if (inv_mode && it.second->type == "$_INV_")
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->connections_.at("\\A")), sigmap(it.second->connections_.at("\\Y"))));
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->get("\\A")), sigmap(it.second->get("\\Y"))));
}
int bits_count = 0;
@ -708,7 +708,7 @@ struct FreduceWorker
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
for (auto &port : drv->connections_)
for (auto &port : drv->connections())
if (ct.cell_output(drv->type, port.first))
sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
@ -719,14 +719,14 @@ struct FreduceWorker
inv_sig = module->addWire(NEW_ID);
RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
inv_cell->connections_["\\A"] = grp[0].bit;
inv_cell->connections_["\\Y"] = inv_sig;
inv_cell->set("\\A", grp[0].bit);
inv_cell->set("\\Y", inv_sig);
}
module->connections_.push_back(RTLIL::SigSig(grp[i].bit, inv_sig));
module->connect(RTLIL::SigSig(grp[i].bit, inv_sig));
}
else
module->connections_.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit));
module->connect(RTLIL::SigSig(grp[i].bit, grp[0].bit));
rewired_sigbits++;
}