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https://github.com/YosysHQ/yosys
synced 2025-07-31 00:13:18 +00:00
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
This commit is contained in:
Clifford Wolf
parent
cd6574ecf6
commit
b7dda72302
61 changed files with 1201 additions and 1201 deletions
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@ -77,8 +77,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
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cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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cell->connections_["\\A"] = sync_low_signals;
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cell->connections_["\\Y"] = sync_low_signals = mod->addWire(NEW_ID);
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cell->set("\\A", sync_low_signals);
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cell->set("\\Y", sync_low_signals = mod->addWire(NEW_ID));
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}
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if (sync_low_signals.size() > 0) {
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@ -86,9 +86,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
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cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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cell->connections_["\\A"] = sync_low_signals;
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cell->connections_["\\Y"] = mod->addWire(NEW_ID);
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sync_high_signals.append(cell->connections_["\\Y"]);
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cell->set("\\A", sync_low_signals);
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cell->set("\\Y", mod->addWire(NEW_ID));
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sync_high_signals.append(cell->get("\\Y"));
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}
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if (sync_high_signals.size() > 1) {
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@ -96,30 +96,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
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cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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cell->connections_["\\A"] = sync_high_signals;
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cell->connections_["\\Y"] = sync_high_signals = mod->addWire(NEW_ID);
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cell->set("\\A", sync_high_signals);
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cell->set("\\Y", sync_high_signals = mod->addWire(NEW_ID));
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}
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RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
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inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
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inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
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inv_cell->connections_["\\A"] = sync_value;
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inv_cell->connections_["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size());
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inv_cell->set("\\A", sync_value);
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inv_cell->set("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
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RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
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mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
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mux_set_cell->connections_["\\A"] = sig_sr_set;
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mux_set_cell->connections_["\\B"] = sync_value;
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mux_set_cell->connections_["\\S"] = sync_high_signals;
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mux_set_cell->connections_["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size());
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mux_set_cell->set("\\A", sig_sr_set);
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mux_set_cell->set("\\B", sync_value);
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mux_set_cell->set("\\S", sync_high_signals);
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mux_set_cell->set("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
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RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
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mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
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mux_clr_cell->connections_["\\A"] = sig_sr_clr;
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mux_clr_cell->connections_["\\B"] = sync_value_inv;
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mux_clr_cell->connections_["\\S"] = sync_high_signals;
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mux_clr_cell->connections_["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size());
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mux_clr_cell->set("\\A", sig_sr_clr);
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mux_clr_cell->set("\\B", sync_value_inv);
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mux_clr_cell->set("\\S", sync_high_signals);
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mux_clr_cell->set("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
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}
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std::stringstream sstr;
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@ -131,11 +131,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
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cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
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cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
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cell->connections_["\\D"] = sig_d;
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cell->connections_["\\Q"] = sig_q;
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cell->connections_["\\CLK"] = clk;
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cell->connections_["\\SET"] = sig_sr_set;
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cell->connections_["\\CLR"] = sig_sr_clr;
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cell->set("\\D", sig_d);
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cell->set("\\Q", sig_q);
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cell->set("\\CLK", clk);
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cell->set("\\SET", sig_sr_set);
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cell->set("\\CLR", sig_sr_clr);
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log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
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cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
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@ -155,22 +155,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
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inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
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inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
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inv_set->connections_["\\A"] = sig_set;
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inv_set->connections_["\\Y"] = sig_set_inv;
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inv_set->set("\\A", sig_set);
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inv_set->set("\\Y", sig_set_inv);
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RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
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mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
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mux_sr_set->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
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mux_sr_set->connections_[set_polarity ? "\\B" : "\\A"] = sig_set;
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mux_sr_set->connections_["\\Y"] = sig_sr_set;
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mux_sr_set->connections_["\\S"] = set;
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mux_sr_set->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
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mux_sr_set->connections()[set_polarity ? "\\B" : "\\A"] = sig_set;
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mux_sr_set->set("\\Y", sig_sr_set);
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mux_sr_set->set("\\S", set);
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RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
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mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
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mux_sr_clr->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
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mux_sr_clr->connections_[set_polarity ? "\\B" : "\\A"] = sig_set_inv;
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mux_sr_clr->connections_["\\Y"] = sig_sr_clr;
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mux_sr_clr->connections_["\\S"] = set;
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mux_sr_clr->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
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mux_sr_clr->connections()[set_polarity ? "\\B" : "\\A"] = sig_set_inv;
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mux_sr_clr->set("\\Y", sig_sr_clr);
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mux_sr_clr->set("\\S", set);
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RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
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cell->attributes = proc->attributes;
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@ -178,11 +178,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
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cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
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cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
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cell->connections_["\\D"] = sig_in;
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cell->connections_["\\Q"] = sig_out;
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cell->connections_["\\CLK"] = clk;
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cell->connections_["\\SET"] = sig_sr_set;
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cell->connections_["\\CLR"] = sig_sr_clr;
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cell->set("\\D", sig_in);
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cell->set("\\Q", sig_out);
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cell->set("\\CLK", clk);
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cell->set("\\SET", sig_sr_set);
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cell->set("\\CLR", sig_sr_clr);
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log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
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clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
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@ -204,11 +204,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_
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}
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
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cell->connections_["\\D"] = sig_in;
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cell->connections_["\\Q"] = sig_out;
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cell->set("\\D", sig_in);
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cell->set("\\Q", sig_out);
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if (arst)
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cell->connections_["\\ARST"] = *arst;
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cell->connections_["\\CLK"] = clk;
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cell->set("\\ARST", *arst);
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cell->set("\\CLK", clk);
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log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
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if (arst)
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@ -296,9 +296,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
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cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
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cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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cell->connections_["\\A"] = inputs;
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cell->connections_["\\B"] = compare;
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cell->connections_["\\Y"] = sync_level->signal;
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cell->set("\\A", inputs);
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cell->set("\\B", compare);
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cell->set("\\Y", sync_level->signal);
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many_async_rules.clear();
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}
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@ -322,7 +322,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
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if (sync_edge || sync_level || many_async_rules.size() > 0)
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log_error("Mixed always event with edge and/or level sensitive events!\n");
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log(" created direct connection (no actual register cell created).\n");
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mod->connections_.push_back(RTLIL::SigSig(sig, insig));
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mod->connect(RTLIL::SigSig(sig, insig));
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continue;
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}
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