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https://github.com/YosysHQ/yosys
synced 2025-04-27 19:05:52 +00:00
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
This commit is contained in:
Clifford Wolf
parent
cd6574ecf6
commit
b7dda72302
61 changed files with 1201 additions and 1201 deletions
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@ -38,7 +38,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
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SigPool all_signals;
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for (auto &it : module->cells)
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for (auto &conn : it.second->connections_) {
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for (auto &conn : it.second->connections()) {
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if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
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driven_signals.add(sigmap(conn.second));
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if (!ct.cell_known(it.second->type) || ct.cell_input(it.second->type, conn.first))
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@ -66,21 +66,21 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
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continue;
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log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
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module->connections_.push_back(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
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module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
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OPT_DID_SOMETHING = true;
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}
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}
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static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
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{
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RTLIL::SigSpec Y = cell->connections_[out_port];
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RTLIL::SigSpec Y = cell->connections()[out_port];
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out_val.extend_u0(Y.size(), false);
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log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
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cell->type.c_str(), cell->name.c_str(), info.c_str(),
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module->name.c_str(), log_signal(Y), log_signal(out_val));
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// ILANG_BACKEND::dump_cell(stderr, "--> ", cell);
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module->connections_.push_back(RTLIL::SigSig(Y, out_val));
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module->connect(RTLIL::SigSig(Y, out_val));
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module->remove(cell);
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OPT_DID_SOMETHING = true;
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did_something = true;
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@ -88,14 +88,14 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i
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static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap)
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{
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std::string b_name = cell->connections_.count("\\B") ? "\\B" : "\\A";
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std::string b_name = cell->connections().count("\\B") ? "\\B" : "\\A";
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bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
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bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
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RTLIL::SigSpec sig_a = sigmap(cell->connections_.at("\\A"));
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RTLIL::SigSpec sig_b = sigmap(cell->connections_.at(b_name));
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RTLIL::SigSpec sig_y = sigmap(cell->connections_.at("\\Y"));
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RTLIL::SigSpec sig_a = sigmap(cell->get("\\A"));
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RTLIL::SigSpec sig_b = sigmap(cell->connections().at(b_name));
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RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y"));
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if (extend_u0) {
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sig_a.extend_u0(sig_y.size(), a_signed);
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@ -160,21 +160,21 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
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RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
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c->connections_["\\A"] = new_a;
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c->set("\\A", new_a);
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c->parameters["\\A_WIDTH"] = new_a.size();
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c->parameters["\\A_SIGNED"] = false;
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if (b_name == "\\B") {
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c->connections_["\\B"] = new_b;
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c->set("\\B", new_b);
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c->parameters["\\B_WIDTH"] = new_b.size();
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c->parameters["\\B_SIGNED"] = false;
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}
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c->connections_["\\Y"] = new_y;
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c->set("\\Y", new_y);
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c->parameters["\\Y_WIDTH"] = new_y->width;
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c->check();
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module->connections_.push_back(new_conn);
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module->connect(new_conn);
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log(" New cell `%s': A=%s", log_id(c), log_signal(new_a));
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if (b_name == "\\B")
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@ -203,8 +203,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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for (auto &cell_it : module->cells)
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if (design->selected(module, cell_it.second)) {
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if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") &&
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cell_it.second->connections_["\\A"].size() == 1 && cell_it.second->connections_["\\Y"].size() == 1)
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invert_map[assign_map(cell_it.second->connections_["\\Y"])] = assign_map(cell_it.second->connections_["\\A"]);
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cell_it.second->get("\\A").size() == 1 && cell_it.second->get("\\Y").size() == 1)
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invert_map[assign_map(cell_it.second->get("\\Y"))] = assign_map(cell_it.second->get("\\A"));
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cells.push_back(cell_it.second);
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}
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@ -222,7 +222,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (cell->type == "$reduce_and")
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{
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RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A"));
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RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
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RTLIL::State new_a = RTLIL::State::S1;
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for (auto &bit : sig_a.to_sigbit_vector())
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@ -240,7 +240,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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cover("opt.opt_const.fine.$reduce_and");
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log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
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cell->connections_.at("\\A") = sig_a = new_a;
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cell->get("\\A") = sig_a = new_a;
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cell->parameters.at("\\A_WIDTH") = 1;
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OPT_DID_SOMETHING = true;
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did_something = true;
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@ -249,7 +249,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool")
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{
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RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A"));
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RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
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RTLIL::State new_a = RTLIL::State::S0;
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for (auto &bit : sig_a.to_sigbit_vector())
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@ -267,7 +267,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type);
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log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
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cell->connections_.at("\\A") = sig_a = new_a;
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cell->get("\\A") = sig_a = new_a;
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cell->parameters.at("\\A_WIDTH") = 1;
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OPT_DID_SOMETHING = true;
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did_something = true;
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@ -276,7 +276,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (cell->type == "$logic_and" || cell->type == "$logic_or")
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{
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RTLIL::SigSpec sig_b = assign_map(cell->connections_.at("\\B"));
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RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
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RTLIL::State new_b = RTLIL::State::S0;
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for (auto &bit : sig_b.to_sigbit_vector())
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@ -294,7 +294,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type);
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log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
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cell->connections_.at("\\B") = sig_b = new_b;
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cell->get("\\B") = sig_b = new_b;
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cell->parameters.at("\\B_WIDTH") = 1;
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OPT_DID_SOMETHING = true;
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did_something = true;
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@ -302,13 +302,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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}
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}
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if (cell->type == "$logic_or" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S1 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S1)) {
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if (cell->type == "$logic_or" && (assign_map(cell->get("\\A")) == RTLIL::State::S1 || assign_map(cell->get("\\B")) == RTLIL::State::S1)) {
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cover("opt.opt_const.one_high");
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replace_cell(module, cell, "one high", "\\Y", RTLIL::State::S1);
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goto next_cell;
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}
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if (cell->type == "$logic_and" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S0 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S0)) {
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if (cell->type == "$logic_and" && (assign_map(cell->get("\\A")) == RTLIL::State::S0 || assign_map(cell->get("\\B")) == RTLIL::State::S0)) {
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cover("opt.opt_const.one_low");
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replace_cell(module, cell, "one low", "\\Y", RTLIL::State::S0);
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goto next_cell;
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@ -320,8 +320,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" ||
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cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
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{
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RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A"));
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RTLIL::SigSpec sig_b = cell->connections_.count("\\B") ? assign_map(cell->connections_.at("\\B")) : RTLIL::SigSpec();
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RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
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RTLIL::SigSpec sig_b = cell->connections().count("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec();
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if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr")
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sig_a = RTLIL::SigSpec();
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@ -342,31 +342,31 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
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replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
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else
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replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections_.at("\\Y").size()));
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replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->get("\\Y").size()));
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goto next_cell;
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}
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}
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if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections_["\\Y"].size() == 1 &&
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invert_map.count(assign_map(cell->connections_["\\A"])) != 0) {
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if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->get("\\Y").size() == 1 &&
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invert_map.count(assign_map(cell->get("\\A"))) != 0) {
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cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type);
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replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections_["\\A"])));
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replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->get("\\A"))));
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goto next_cell;
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}
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if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->connections_["\\S"])) != 0) {
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if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->get("\\S"))) != 0) {
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cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type);
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RTLIL::SigSpec tmp = cell->connections_["\\A"];
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cell->connections_["\\A"] = cell->connections_["\\B"];
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cell->connections_["\\B"] = tmp;
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cell->connections_["\\S"] = invert_map.at(assign_map(cell->connections_["\\S"]));
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RTLIL::SigSpec tmp = cell->get("\\A");
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cell->set("\\A", cell->get("\\B"));
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cell->set("\\B", tmp);
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cell->set("\\S", invert_map.at(assign_map(cell->get("\\S"))));
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OPT_DID_SOMETHING = true;
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did_something = true;
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goto next_cell;
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}
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if (cell->type == "$_INV_") {
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RTLIL::SigSpec input = cell->connections_["\\A"];
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RTLIL::SigSpec input = cell->get("\\A");
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assign_map.apply(input);
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if (input.match("1")) ACTION_DO_Y(0);
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if (input.match("0")) ACTION_DO_Y(1);
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@ -375,8 +375,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (cell->type == "$_AND_") {
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RTLIL::SigSpec input;
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input.append(cell->connections_["\\B"]);
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input.append(cell->connections_["\\A"]);
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input.append(cell->get("\\B"));
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input.append(cell->get("\\A"));
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assign_map.apply(input);
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if (input.match(" 0")) ACTION_DO_Y(0);
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if (input.match("0 ")) ACTION_DO_Y(0);
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@ -394,8 +394,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (cell->type == "$_OR_") {
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RTLIL::SigSpec input;
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input.append(cell->connections_["\\B"]);
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input.append(cell->connections_["\\A"]);
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input.append(cell->get("\\B"));
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input.append(cell->get("\\A"));
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assign_map.apply(input);
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if (input.match(" 1")) ACTION_DO_Y(1);
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if (input.match("1 ")) ACTION_DO_Y(1);
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@ -413,8 +413,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (cell->type == "$_XOR_") {
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RTLIL::SigSpec input;
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input.append(cell->connections_["\\B"]);
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input.append(cell->connections_["\\A"]);
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input.append(cell->get("\\B"));
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input.append(cell->get("\\A"));
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assign_map.apply(input);
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if (input.match("00")) ACTION_DO_Y(0);
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if (input.match("01")) ACTION_DO_Y(1);
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@ -428,9 +428,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (cell->type == "$_MUX_") {
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RTLIL::SigSpec input;
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input.append(cell->connections_["\\S"]);
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input.append(cell->connections_["\\B"]);
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input.append(cell->connections_["\\A"]);
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input.append(cell->get("\\S"));
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input.append(cell->get("\\B"));
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input.append(cell->get("\\A"));
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assign_map.apply(input);
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if (input.extract(2, 1) == input.extract(1, 1))
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ACTION_DO("\\Y", input.extract(2, 1));
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@ -440,9 +440,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (input.match("10 ")) {
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cover("opt.opt_const.mux_to_inv");
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cell->type = "$_INV_";
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cell->connections_["\\A"] = input.extract(0, 1);
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cell->connections_.erase("\\B");
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cell->connections_.erase("\\S");
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cell->set("\\A", input.extract(0, 1));
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cell->connections().erase("\\B");
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cell->connections().erase("\\S");
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goto next_cell;
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}
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if (input.match("11 ")) ACTION_DO_Y(1);
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@ -459,8 +459,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex")
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{
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RTLIL::SigSpec a = cell->connections_["\\A"];
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RTLIL::SigSpec b = cell->connections_["\\B"];
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RTLIL::SigSpec a = cell->get("\\A");
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RTLIL::SigSpec b = cell->get("\\B");
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if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
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int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
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@ -495,8 +495,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (new_a.size() < a.size() || new_b.size() < b.size()) {
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cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type);
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cell->connections_["\\A"] = new_a;
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cell->connections_["\\B"] = new_b;
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cell->set("\\A", new_a);
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cell->set("\\B", new_b);
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cell->parameters["\\A_WIDTH"] = new_a.size();
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cell->parameters["\\B_WIDTH"] = new_b.size();
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}
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@ -505,24 +505,24 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
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cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
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{
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RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]);
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RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
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RTLIL::SigSpec a = assign_map(cell->get("\\A"));
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||||
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
|
||||
|
||||
if (a.is_fully_const()) {
|
||||
cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type);
|
||||
std::swap(cell->connections_["\\A"], cell->connections_["\\B"]);
|
||||
std::swap(cell->get("\\A"), cell->get("\\B"));
|
||||
}
|
||||
|
||||
if (b.is_fully_const()) {
|
||||
if (b.as_bool() == (cell->type == "$eq")) {
|
||||
RTLIL::SigSpec input = b;
|
||||
ACTION_DO("\\Y", cell->connections_["\\A"]);
|
||||
ACTION_DO("\\Y", cell->get("\\A"));
|
||||
} else {
|
||||
cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type);
|
||||
cell->type = "$not";
|
||||
cell->parameters.erase("\\B_WIDTH");
|
||||
cell->parameters.erase("\\B_SIGNED");
|
||||
cell->connections_.erase("\\B");
|
||||
cell->connections().erase("\\B");
|
||||
}
|
||||
goto next_cell;
|
||||
}
|
||||
|
|
@ -536,8 +536,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
|
||||
if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor")
|
||||
{
|
||||
RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]);
|
||||
RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
|
||||
RTLIL::SigSpec a = assign_map(cell->get("\\A"));
|
||||
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
|
||||
|
||||
if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false)
|
||||
identity_wrt_b = true;
|
||||
|
|
@ -548,7 +548,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
|
||||
if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr")
|
||||
{
|
||||
RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
|
||||
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
|
||||
|
||||
if (b.is_fully_const() && b.as_bool() == false)
|
||||
identity_wrt_a = true, identity_bu0 = true;
|
||||
|
|
@ -556,8 +556,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
|
||||
if (cell->type == "$mul")
|
||||
{
|
||||
RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]);
|
||||
RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
|
||||
RTLIL::SigSpec a = assign_map(cell->get("\\A"));
|
||||
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
|
||||
|
||||
if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1)
|
||||
identity_wrt_b = true;
|
||||
|
|
@ -568,7 +568,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
|
||||
if (cell->type == "$div")
|
||||
{
|
||||
RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
|
||||
RTLIL::SigSpec b = assign_map(cell->get("\\B"));
|
||||
|
||||
if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
|
||||
identity_wrt_a = true;
|
||||
|
|
@ -585,13 +585,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
|
||||
|
||||
if (!identity_wrt_a) {
|
||||
cell->connections_.at("\\A") = cell->connections_.at("\\B");
|
||||
cell->get("\\A") = cell->get("\\B");
|
||||
cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
|
||||
cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
|
||||
}
|
||||
|
||||
cell->type = identity_bu0 ? "$bu0" : "$pos";
|
||||
cell->connections_.erase("\\B");
|
||||
cell->connections().erase("\\B");
|
||||
cell->parameters.erase("\\B_WIDTH");
|
||||
cell->parameters.erase("\\B_SIGNED");
|
||||
cell->check();
|
||||
|
|
@ -603,18 +603,18 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
}
|
||||
|
||||
if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
|
||||
cell->connections_["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) {
|
||||
cell->get("\\A") == RTLIL::SigSpec(0, 1) && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
|
||||
cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type);
|
||||
replace_cell(module, cell, "mux_bool", "\\Y", cell->connections_["\\S"]);
|
||||
replace_cell(module, cell, "mux_bool", "\\Y", cell->get("\\S"));
|
||||
goto next_cell;
|
||||
}
|
||||
|
||||
if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
|
||||
cell->connections_["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(0, 1)) {
|
||||
cell->get("\\A") == RTLIL::SigSpec(1, 1) && cell->get("\\B") == RTLIL::SigSpec(0, 1)) {
|
||||
cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type);
|
||||
cell->connections_["\\A"] = cell->connections_["\\S"];
|
||||
cell->connections_.erase("\\B");
|
||||
cell->connections_.erase("\\S");
|
||||
cell->set("\\A", cell->get("\\S"));
|
||||
cell->connections().erase("\\B");
|
||||
cell->connections().erase("\\S");
|
||||
if (cell->type == "$mux") {
|
||||
cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
|
||||
cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
|
||||
|
|
@ -628,10 +628,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
goto next_cell;
|
||||
}
|
||||
|
||||
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\A"] == RTLIL::SigSpec(0, 1)) {
|
||||
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1)) {
|
||||
cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type);
|
||||
cell->connections_["\\A"] = cell->connections_["\\S"];
|
||||
cell->connections_.erase("\\S");
|
||||
cell->set("\\A", cell->get("\\S"));
|
||||
cell->connections().erase("\\S");
|
||||
if (cell->type == "$mux") {
|
||||
cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
|
||||
cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
|
||||
|
|
@ -647,10 +647,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
goto next_cell;
|
||||
}
|
||||
|
||||
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) {
|
||||
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
|
||||
cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type);
|
||||
cell->connections_["\\B"] = cell->connections_["\\S"];
|
||||
cell->connections_.erase("\\S");
|
||||
cell->set("\\B", cell->get("\\S"));
|
||||
cell->connections().erase("\\S");
|
||||
if (cell->type == "$mux") {
|
||||
cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
|
||||
cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
|
||||
|
|
@ -668,22 +668,22 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
|
||||
if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
|
||||
RTLIL::SigSpec new_a, new_b, new_s;
|
||||
int width = cell->connections_.at("\\A").size();
|
||||
if ((cell->connections_.at("\\A").is_fully_undef() && cell->connections_.at("\\B").is_fully_undef()) ||
|
||||
cell->connections_.at("\\S").is_fully_undef()) {
|
||||
int width = cell->get("\\A").size();
|
||||
if ((cell->get("\\A").is_fully_undef() && cell->get("\\B").is_fully_undef()) ||
|
||||
cell->get("\\S").is_fully_undef()) {
|
||||
cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type);
|
||||
replace_cell(module, cell, "mux_undef", "\\Y", cell->connections_.at("\\A"));
|
||||
replace_cell(module, cell, "mux_undef", "\\Y", cell->get("\\A"));
|
||||
goto next_cell;
|
||||
}
|
||||
for (int i = 0; i < cell->connections_.at("\\S").size(); i++) {
|
||||
RTLIL::SigSpec old_b = cell->connections_.at("\\B").extract(i*width, width);
|
||||
RTLIL::SigSpec old_s = cell->connections_.at("\\S").extract(i, 1);
|
||||
for (int i = 0; i < cell->get("\\S").size(); i++) {
|
||||
RTLIL::SigSpec old_b = cell->get("\\B").extract(i*width, width);
|
||||
RTLIL::SigSpec old_s = cell->get("\\S").extract(i, 1);
|
||||
if (old_b.is_fully_undef() || old_s.is_fully_undef())
|
||||
continue;
|
||||
new_b.append(old_b);
|
||||
new_s.append(old_s);
|
||||
}
|
||||
new_a = cell->connections_.at("\\A");
|
||||
new_a = cell->get("\\A");
|
||||
if (new_a.is_fully_undef() && new_s.size() > 0) {
|
||||
new_a = new_b.extract((new_s.size()-1)*width, width);
|
||||
new_b = new_b.extract(0, (new_s.size()-1)*width);
|
||||
|
|
@ -699,11 +699,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
replace_cell(module, cell, "mux_sel01", "\\Y", new_s);
|
||||
goto next_cell;
|
||||
}
|
||||
if (cell->connections_.at("\\S").size() != new_s.size()) {
|
||||
if (cell->get("\\S").size() != new_s.size()) {
|
||||
cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type);
|
||||
cell->connections_.at("\\A") = new_a;
|
||||
cell->connections_.at("\\B") = new_b;
|
||||
cell->connections_.at("\\S") = new_s;
|
||||
cell->get("\\A") = new_a;
|
||||
cell->get("\\B") = new_b;
|
||||
cell->get("\\S") = new_s;
|
||||
if (new_s.size() > 1) {
|
||||
cell->type = "$pmux";
|
||||
cell->parameters["\\S_WIDTH"] = new_s.size();
|
||||
|
|
@ -718,7 +718,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
|
||||
#define FOLD_1ARG_CELL(_t) \
|
||||
if (cell->type == "$" #_t) { \
|
||||
RTLIL::SigSpec a = cell->connections_["\\A"]; \
|
||||
RTLIL::SigSpec a = cell->get("\\A"); \
|
||||
assign_map.apply(a); \
|
||||
if (a.is_fully_const()) { \
|
||||
RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
|
||||
|
|
@ -732,8 +732,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
}
|
||||
#define FOLD_2ARG_CELL(_t) \
|
||||
if (cell->type == "$" #_t) { \
|
||||
RTLIL::SigSpec a = cell->connections_["\\A"]; \
|
||||
RTLIL::SigSpec b = cell->connections_["\\B"]; \
|
||||
RTLIL::SigSpec a = cell->get("\\A"); \
|
||||
RTLIL::SigSpec b = cell->get("\\B"); \
|
||||
assign_map.apply(a), assign_map.apply(b); \
|
||||
if (a.is_fully_const() && b.is_fully_const()) { \
|
||||
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
|
||||
|
|
@ -787,13 +787,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
|
||||
// be very conservative with optimizing $mux cells as we do not want to break mux trees
|
||||
if (cell->type == "$mux") {
|
||||
RTLIL::SigSpec input = assign_map(cell->connections_["\\S"]);
|
||||
RTLIL::SigSpec inA = assign_map(cell->connections_["\\A"]);
|
||||
RTLIL::SigSpec inB = assign_map(cell->connections_["\\B"]);
|
||||
RTLIL::SigSpec input = assign_map(cell->get("\\S"));
|
||||
RTLIL::SigSpec inA = assign_map(cell->get("\\A"));
|
||||
RTLIL::SigSpec inB = assign_map(cell->get("\\B"));
|
||||
if (input.is_fully_const())
|
||||
ACTION_DO("\\Y", input.as_bool() ? cell->connections_["\\B"] : cell->connections_["\\A"]);
|
||||
ACTION_DO("\\Y", input.as_bool() ? cell->get("\\B") : cell->get("\\A"));
|
||||
else if (inA == inB)
|
||||
ACTION_DO("\\Y", cell->connections_["\\A"]);
|
||||
ACTION_DO("\\Y", cell->get("\\A"));
|
||||
}
|
||||
|
||||
if (!keepdc && cell->type == "$mul")
|
||||
|
|
@ -802,9 +802,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
bool b_signed = cell->parameters["\\B_SIGNED"].as_bool();
|
||||
bool swapped_ab = false;
|
||||
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]);
|
||||
RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]);
|
||||
RTLIL::SigSpec sig_y = assign_map(cell->connections_["\\Y"]);
|
||||
RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
|
||||
RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
|
||||
RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
|
||||
|
||||
if (sig_b.is_fully_const() && sig_b.size() <= 32)
|
||||
std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true;
|
||||
|
|
@ -820,7 +820,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
|
||||
cell->name.c_str(), module->name.c_str());
|
||||
|
||||
module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
|
||||
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
|
||||
module->remove(cell);
|
||||
|
||||
OPT_DID_SOMETHING = true;
|
||||
|
|
@ -840,7 +840,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
a_val, cell->name.c_str(), module->name.c_str(), i);
|
||||
|
||||
if (!swapped_ab) {
|
||||
cell->connections_["\\A"] = cell->connections_["\\B"];
|
||||
cell->set("\\A", cell->get("\\B"));
|
||||
cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"];
|
||||
cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"];
|
||||
}
|
||||
|
|
@ -853,7 +853,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
|
|||
cell->type = "$shl";
|
||||
cell->parameters["\\B_WIDTH"] = SIZE(new_b);
|
||||
cell->parameters["\\B_SIGNED"] = false;
|
||||
cell->connections_["\\B"] = new_b;
|
||||
cell->set("\\B", new_b);
|
||||
cell->check();
|
||||
|
||||
OPT_DID_SOMETHING = true;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue