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Changed users of cell->connections_ to the new API (sed command)

git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
This commit is contained in:
Clifford Wolf 2014-07-26 14:32:50 +02:00
parent cd6574ecf6
commit b7dda72302
61 changed files with 1201 additions and 1201 deletions

View file

@ -54,9 +54,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
cell->connections_["\\CLK"] = memory->connections_.at("\\RD_CLK").extract(i, 1);
cell->connections_["\\ADDR"] = memory->connections_.at("\\RD_ADDR").extract(i*abits, abits);
cell->connections_["\\DATA"] = memory->connections_.at("\\RD_DATA").extract(i*mem->width, mem->width);
cell->set("\\CLK", memory->get("\\RD_CLK").extract(i, 1));
cell->set("\\ADDR", memory->get("\\RD_ADDR").extract(i*abits, abits));
cell->set("\\DATA", memory->get("\\RD_DATA").extract(i*mem->width, mem->width));
}
for (int i = 0; i < num_wr_ports; i++)
@ -68,10 +68,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
cell->parameters["\\PRIORITY"] = i;
cell->connections_["\\CLK"] = memory->connections_.at("\\WR_CLK").extract(i, 1);
cell->connections_["\\EN"] = memory->connections_.at("\\WR_EN").extract(i*mem->width, mem->width);
cell->connections_["\\ADDR"] = memory->connections_.at("\\WR_ADDR").extract(i*abits, abits);
cell->connections_["\\DATA"] = memory->connections_.at("\\WR_DATA").extract(i*mem->width, mem->width);
cell->set("\\CLK", memory->get("\\WR_CLK").extract(i, 1));
cell->set("\\EN", memory->get("\\WR_EN").extract(i*mem->width, mem->width));
cell->set("\\ADDR", memory->get("\\WR_ADDR").extract(i*abits, abits));
cell->set("\\DATA", memory->get("\\WR_DATA").extract(i*mem->width, mem->width));
}
module->remove(memory);