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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
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parent
cd6574ecf6
commit
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61 changed files with 1201 additions and 1201 deletions
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@ -54,9 +54,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
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cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
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cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
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cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
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cell->connections_["\\CLK"] = memory->connections_.at("\\RD_CLK").extract(i, 1);
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cell->connections_["\\ADDR"] = memory->connections_.at("\\RD_ADDR").extract(i*abits, abits);
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cell->connections_["\\DATA"] = memory->connections_.at("\\RD_DATA").extract(i*mem->width, mem->width);
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cell->set("\\CLK", memory->get("\\RD_CLK").extract(i, 1));
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cell->set("\\ADDR", memory->get("\\RD_ADDR").extract(i*abits, abits));
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cell->set("\\DATA", memory->get("\\RD_DATA").extract(i*mem->width, mem->width));
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}
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for (int i = 0; i < num_wr_ports; i++)
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@ -68,10 +68,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
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cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
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cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
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cell->parameters["\\PRIORITY"] = i;
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cell->connections_["\\CLK"] = memory->connections_.at("\\WR_CLK").extract(i, 1);
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cell->connections_["\\EN"] = memory->connections_.at("\\WR_EN").extract(i*mem->width, mem->width);
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cell->connections_["\\ADDR"] = memory->connections_.at("\\WR_ADDR").extract(i*abits, abits);
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cell->connections_["\\DATA"] = memory->connections_.at("\\WR_DATA").extract(i*mem->width, mem->width);
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cell->set("\\CLK", memory->get("\\WR_CLK").extract(i, 1));
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cell->set("\\EN", memory->get("\\WR_EN").extract(i*mem->width, mem->width));
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cell->set("\\ADDR", memory->get("\\WR_ADDR").extract(i*abits, abits));
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cell->set("\\DATA", memory->get("\\WR_DATA").extract(i*mem->width, mem->width));
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}
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module->remove(memory);
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