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https://github.com/YosysHQ/yosys
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
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parent
cd6574ecf6
commit
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61 changed files with 1201 additions and 1201 deletions
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@ -52,8 +52,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
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for (auto &cellport : cellport_list) {
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if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y")
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return false;
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RTLIL::SigSpec sig_a = assign_map(cellport.first->connections_["\\A"]);
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RTLIL::SigSpec sig_b = assign_map(cellport.first->connections_["\\B"]);
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RTLIL::SigSpec sig_a = assign_map(cellport.first->get("\\A"));
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RTLIL::SigSpec sig_b = assign_map(cellport.first->get("\\B"));
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if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
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return false;
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for (int i = 0; i < sig_b.size(); i += sig_a.size())
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@ -80,14 +80,14 @@ static bool check_state_users(RTLIL::SigSpec sig)
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continue;
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if (cellport.second != "\\A" && cellport.second != "\\B")
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return false;
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if (cell->connections_.count("\\A") == 0 || cell->connections_.count("\\B") == 0 || cell->connections_.count("\\Y") == 0)
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if (cell->connections().count("\\A") == 0 || cell->connections().count("\\B") == 0 || cell->connections().count("\\Y") == 0)
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return false;
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for (auto &port_it : cell->connections_)
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for (auto &port_it : cell->connections())
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if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
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return false;
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if (assign_map(cell->connections_["\\A"]) == sig && cell->connections_["\\B"].is_fully_const())
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if (assign_map(cell->get("\\A")) == sig && cell->get("\\B").is_fully_const())
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continue;
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if (assign_map(cell->connections_["\\B"]) == sig && cell->connections_["\\A"].is_fully_const())
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if (assign_map(cell->get("\\B")) == sig && cell->get("\\A").is_fully_const())
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continue;
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return false;
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}
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@ -109,8 +109,8 @@ static void detect_fsm(RTLIL::Wire *wire)
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continue;
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muxtree_cells.clear();
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SigPool recursion_monitor;
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RTLIL::SigSpec sig_q = assign_map(cellport.first->connections_["\\Q"]);
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RTLIL::SigSpec sig_d = assign_map(cellport.first->connections_["\\D"]);
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RTLIL::SigSpec sig_q = assign_map(cellport.first->get("\\Q"));
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RTLIL::SigSpec sig_d = assign_map(cellport.first->get("\\D"));
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if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) {
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log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str());
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wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
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@ -160,7 +160,7 @@ struct FsmDetectPass : public Pass {
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sig2user.clear();
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sig_at_port.clear();
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for (auto &cell_it : module->cells)
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for (auto &conn_it : cell_it.second->connections_) {
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for (auto &conn_it : cell_it.second->connections()) {
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if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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