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Changed users of cell->connections_ to the new API (sed command)

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git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
This commit is contained in:
Clifford Wolf 2014-07-26 14:32:50 +02:00
parent cd6574ecf6
commit b7dda72302
61 changed files with 1201 additions and 1201 deletions
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20
passes/cmds/splice.cc
View file

@ -74,9 +74,9 @@ struct SpliceWorker
cell->parameters["\\OFFSET"] = offset;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig.size();
cell->connections_["\\A"] = sig_a;
cell->connections_["\\Y"] = module->addWire(NEW_ID, sig.size());
new_sig = cell->connections_["\\Y"];
cell->set("\\A", sig_a);
cell->set("\\Y", module->addWire(NEW_ID, sig.size()));
new_sig = cell->get("\\Y");
}
sliced_signals_cache[sig] = new_sig;
@ -130,10 +130,10 @@ struct SpliceWorker
RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
cell->parameters["\\A_WIDTH"] = new_sig.size();
cell->parameters["\\B_WIDTH"] = sig2.size();
cell->connections_["\\A"] = new_sig;
cell->connections_["\\B"] = sig2;
cell->connections_["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size());
new_sig = cell->connections_["\\Y"];
cell->set("\\A", new_sig);
cell->set("\\B", sig2);
cell->set("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
new_sig = cell->get("\\Y");
}
spliced_signals_cache[sig] = new_sig;
@ -159,7 +159,7 @@ struct SpliceWorker
}
for (auto &it : module->cells)
for (auto &conn : it.second->connections_)
for (auto &conn : it.second->connections())
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
RTLIL::SigSpec sig = sigmap(conn.second);
driven_chunks.insert(sig);
@ -182,7 +182,7 @@ struct SpliceWorker
for (auto &it : module->cells) {
if (!sel_by_wire && !design->selected(module, it.second))
continue;
for (auto &conn : it.second->connections_)
for (auto &conn : it.second->connections())
if (ct.cell_input(it.second->type, conn.first)) {
if (ports.size() > 0 && !ports.count(conn.first))
continue;
@ -232,7 +232,7 @@ struct SpliceWorker
it.first->port_output = false;
module->add(it.first);
module->add(new_port);
module->connections_.push_back(RTLIL::SigSig(new_port, it.second));
module->connect(RTLIL::SigSig(new_port, it.second));
}
}
};