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Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map

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Cleanup +/xilinx/arith_map.v
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Eddie Hung 2020-01-18 09:11:52 -08:00 • committed by GitHub
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2 changed files with 88 additions and 125 deletions
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207
techlibs/xilinx/arith_map.v
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@ -33,7 +33,21 @@ module _80_xilinx_lcu (P, G, CI, CO);
genvar i; genvar i;
`ifdef _CLB_CARRY `ifdef _EXPLICIT_CARRY
wire [WIDTH-1:0] C = {CO, CI};
wire [WIDTH-1:0] S = P & ~G;
generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(G[i]),
.S(S[i]),
.O(CO[i])
);
end endgenerate
`else
localparam CARRY4_COUNT = (WIDTH + 3) / 4; localparam CARRY4_COUNT = (WIDTH + 3) / 4;
localparam MAX_WIDTH = CARRY4_COUNT * 4; localparam MAX_WIDTH = CARRY4_COUNT * 4;
@ -53,9 +67,9 @@ module _80_xilinx_lcu (P, G, CI, CO);
( (
.CYINIT(CI), .CYINIT(CI),
.CI (1'd0), .CI (1'd0),
.DI (G [(Y_WIDTH - 1):i*4]), .DI (G [(WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]), .S (S [(WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4]), .CO (CO[(WIDTH - 1):i*4]),
); );
// Another one // Another one
end else begin end else begin
@ -63,9 +77,9 @@ module _80_xilinx_lcu (P, G, CI, CO);
( (
.CYINIT(1'd0), .CYINIT(1'd0),
.CI (C [i*4 - 1]), .CI (C [i*4 - 1]),
.DI (G [(Y_WIDTH - 1):i*4]), .DI (G [(WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]), .S (S [(WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4]), .CO (CO[(WIDTH - 1):i*4]),
); );
end end
@ -97,34 +111,6 @@ module _80_xilinx_lcu (P, G, CI, CO);
end end
end endgenerate end endgenerate
`elsif _EXPLICIT_CARRY
wire [WIDTH-1:0] C = {CO, CI};
wire [WIDTH-1:0] S = P & ~G;
generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(G[i]),
.S(S[i]),
.O(CO[i])
);
end endgenerate
`else
wire [WIDTH-1:0] C = {CO, CI};
wire [WIDTH-1:0] S = P & ~G;
generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(G[i]),
.S(S[i]),
.O(CO[i])
);
end endgenerate
`endif `endif
endmodule endmodule
@ -161,79 +147,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
genvar i; genvar i;
`ifdef _CLB_CARRY `ifdef _EXPLICIT_CARRY
localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
wire [MAX_WIDTH-1:0] C = CO;
genvar i;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
// Partially occupied CARRY4
if ((i+1)*4 > Y_WIDTH) begin
// First one
if (i == 0) begin
CARRY4 carry4_1st_part
(
.CYINIT(CI),
.CI (1'd0),
.DI (DI[(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.O (Y [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4])
);
// Another one
end else begin
CARRY4 carry4_part
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.O (Y [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4])
);
end
// Fully occupied CARRY4
end else begin
// First one
if (i == 0) begin
CARRY4 carry4_1st_full
(
.CYINIT(CI),
.CI (1'd0),
.DI (DI[((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.O (Y [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4])
);
// Another one
end else begin
CARRY4 carry4_full
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.O (Y [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4])
);
end
end
end endgenerate
`elsif _EXPLICIT_CARRY
wire [Y_WIDTH-1:0] S = AA ^ BB; wire [Y_WIDTH-1:0] S = AA ^ BB;
wire [Y_WIDTH-1:0] DI = AA & BB; wire [Y_WIDTH-1:0] DI = AA & BB;
@ -333,23 +247,74 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
`else `else
wire [Y_WIDTH-1:0] S = AA ^ BB; localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
wire [Y_WIDTH-1:0] DI = AA & BB; localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
wire [Y_WIDTH-1:0] C = {CO, CI}; wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice wire [MAX_WIDTH-1:0] C = CO;
MUXCY muxcy (
.CI(C[i]), genvar i;
.DI(DI[i]), generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
.S(S[i]),
.O(CO[i]) // Partially occupied CARRY4
if ((i+1)*4 > Y_WIDTH) begin
// First one
if (i == 0) begin
CARRY4 carry4_1st_part
(
.CYINIT(CI),
.CI (1'd0),
.DI (DI[(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.O (Y [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4])
); );
XORCY xorcy ( // Another one
.CI(C[i]), end else begin
.LI(S[i]), CARRY4 carry4_part
.O(Y[i]) (
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.O (Y [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4])
); );
end
// Fully occupied CARRY4
end else begin
// First one
if (i == 0) begin
CARRY4 carry4_1st_full
(
.CYINIT(CI),
.CI (1'd0),
.DI (DI[((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.O (Y [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4])
);
// Another one
end else begin
CARRY4 carry4_full
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.O (Y [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4])
);
end
end
end endgenerate end endgenerate
`endif `endif

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -518,8 +518,6 @@ struct SynthXilinxPass : public ScriptPass
techmap_args += " -map +/xilinx/arith_map.v"; techmap_args += " -map +/xilinx/arith_map.v";
if (vpr) if (vpr)
techmap_args += " -D _EXPLICIT_CARRY"; techmap_args += " -D _EXPLICIT_CARRY";
else
techmap_args += " -D _CLB_CARRY";
} }
run("techmap " + techmap_args); run("techmap " + techmap_args);
run("opt -fast"); run("opt -fast");