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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

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Ahmed Irfan 2014-01-20 09:58:04 +01:00
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manual/CHAPTER_CellLib.tex
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@ -418,3 +418,7 @@ from the gate level logic network can be mapped to physical flip-flop cells from
pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC \citeweblink{ABC}
using the {\tt abc} pass.
\begin{fixme}
Add information about {\tt \$assert} cells.
\end{fixme}