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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.

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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-06-04 10:42:42 +02:00
parent 5739cf5265
commit b79bd5b3ca
4 changed files with 46 additions and 0 deletions
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21
tests/various/attrib07_func_call.v Normal file
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function [7:0] do_add;
input [7:0] inp_a;
input [7:0] inp_b;
do_add = inp_a + inp_b;
endfunction
module foo(clk, rst, inp_a, inp_b, out);
input wire clk;
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
output wire [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
else out <= do_add (* combinational_adder *) (inp_a, inp_b);
endmodule