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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.

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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-06-04 10:42:42 +02:00
parent 5739cf5265
commit b79bd5b3ca
4 changed files with 46 additions and 0 deletions
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21
tests/various/attrib05_port_conn.v Normal file
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module bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
endmodule