mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

cxxrtl: elide $pmux cells.

Browse source 
On Minerva, this improves runtime by around 10%, mostly by ensuring
that the logic driving FFs is packed into edge conditionals.
This commit is contained in:
whitequark 2020-06-12 02:40:30 +00:00
parent a1785e988b
commit b793e4753b
1 changed files with 16 additions and 30 deletions
Download patch file Download diff file Expand all files Collapse all files

46
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -197,7 +197,7 @@ bool is_extending_cell(RTLIL::IdString type)
bool is_elidable_cell(RTLIL::IdString type)
{
return is_unary_cell(type) || is_binary_cell(type) || type.in(
ID($mux), ID($concat), ID($slice));
ID($mux), ID($concat), ID($slice), ID($pmux));
}
bool is_sync_ff_cell(RTLIL::IdString type)
@ -942,6 +942,21 @@ struct CxxrtlWorker {
f << " : ";
dump_sigspec_rhs(cell->getPort(ID::A));
f << ")";
// Parallel (one-hot) muxes
} else if (cell->type == ID($pmux)) {
int width = cell->getParam(ID::WIDTH).as_int();
int s_width = cell->getParam(ID::S_WIDTH).as_int();
for (int part = 0; part < s_width; part++) {
f << "(";
dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
f << " ? ";
dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
f << " : ";
}
dump_sigspec_rhs(cell->getPort(ID::A));
for (int part = 0; part < s_width; part++) {
f << ")";
}
// Concats
} else if (cell->type == ID($concat)) {
dump_sigspec_rhs(cell->getPort(ID::B));
@ -1008,35 +1023,6 @@ struct CxxrtlWorker {
f << " = ";
dump_cell_elided(cell);
f << ";\n";
// Parallel (one-hot) muxes
} else if (cell->type == ID($pmux)) {
int width = cell->getParam(ID::WIDTH).as_int();
int s_width = cell->getParam(ID::S_WIDTH).as_int();
bool first = true;
for (int part = 0; part < s_width; part++) {
f << (first ? indent : " else ");
first = false;
f << "if (";
dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
f << ") {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Y));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
f << ";\n";
dec_indent();
f << indent << "}";
}
f << " else {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Y));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::A));
f << ";\n";
dec_indent();
f << indent << "}\n";
// Flip-flops
} else if (is_ff_cell(cell->type)) {
if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {