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Allow POs to be PIs in XAIG

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This commit is contained in:
Eddie Hung 2019-04-22 11:22:29 -07:00
parent 2c6358ea25
commit b780c0a7de
1 changed files with 4 additions and 7 deletions
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9
backends/aiger/xaiger.cc
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@ -161,12 +161,8 @@ struct XAigerWriter
} }
} }
for (auto bit : input_bits) { for (auto bit : input_bits)
if (!bit.wire->port_output)
undriven_bits.erase(bit); undriven_bits.erase(bit);
// Erase POs that are also PIs
output_bits.erase(bit);
}
for (auto bit : output_bits) for (auto bit : output_bits)
if (!bit.wire->port_input) if (!bit.wire->port_input)
@ -275,7 +271,8 @@ struct XAigerWriter
} }
} }
} }
if (!abc_box_seen) abc_box_seen = inst_module->attributes.count("\\abc_box_id"); if (!abc_box_seen)
abc_box_seen = inst_module->attributes.count("\\abc_box_id");
ff_bits.emplace_back(d, q); ff_bits.emplace_back(d, q);
undriven_bits.erase(q); undriven_bits.erase(q);