mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-18 14:44:23 +00:00
Code Activity

add $priority cell

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-01-09 18:43:15 +01:00
parent c7b839ef5a
commit b72eaf5de5
9 changed files with 136 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

16
techlibs/common/simlib.v
View file

@ -3250,3 +3250,19 @@ parameter WIDTH = 0;
inout [WIDTH-1:0] Y;
endmodule
// --------------------------------------------------------
//-
//- $priority (A, Y)
//* group unary
//-
//- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set.
//-
module \$priority (A, Y);
parameter WIDTH = 8;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
assign Y = A & (~A + 1);
endmodule