Merge 2eb1051cca into dc77140275

tests/opt/splitlarge_wide_op.tcl

@@ -0,0 +1,71 @@
+proc op_name {op_number} {
+	set op [expr $op_number >> 2]
+	set b_signed [expr {$op_number & 1 ? "signed": "unsigned"}]
+	set a_signed [expr {(($op_number & 2) >> 1) ? "signed": "unsigned"}]
+	set cell "unknown"
+	if { "$op" == "0" } {
+		set cell "\$add"
+	} elseif { "$op" == "1" } {
+		set cell "\$sub"
+	}
+	return "$cell (a $a_signed, b $b_signed)"
+}
+
+proc predict_adder_count {in_width max_width op_number} {
+	set b_signed [expr {$op_number & 1}]
+	set a_signed [expr {($op_number & 2) >> 1}]
+	set a_width [expr {$in_width + $a_signed}]
+	set b_width [expr {$in_width + $b_signed}]
+
+	set adder_width [expr {max($a_width, $b_width)}]
+	set adder_queue [list]
+
+	if {$adder_width > $max_width} {
+			lappend adder_queue $adder_width
+	}
+
+	set adder_count 1
+
+	while {[llength $adder_queue] > 0} {
+			set current [lindex $adder_queue end]
+			set adder_queue [lrange $adder_queue 0 end-1]
+
+			incr adder_count 2 ;  # one changed adder, two new adders
+
+			set low [expr {$current / 2}]
+			set high [expr {$current - $low}]
+			set carry [expr {$high + 1}]
+
+			if {$low > $max_width} {
+					lappend adder_queue $low
+			}
+			if {$high > $max_width} {
+					lappend adder_queue $high
+			}
+			if {$carry > $max_width} {
+					lappend adder_queue $carry
+			}
+	}
+	return $adder_count
+}
+
+yosys -import
+log -header "splitlarge"
+log -push
+for {set i 0} {$i < 8} {incr i} {
+	log -header "[op_name $i]"
+	log -push
+	design -reset
+	read_verilog splitlarge_wide_op.v
+	hierarchy -top wide_op
+	chparam -set width 1024 -set op $i wide_op
+	yosys proc
+	simplemap
+equiv_opt -assert splitlarge
+yosys splitlarge
+	yosys select -assert-none r:A_WIDTH>128
+	yosys select -assert-none r:B_WIDTH>128
+	yosys select -assert-count [predict_adder_count 1024 128 $i] r:A_WIDTH
+	log -pop
+}
+log -pop

tests/opt/splitlarge_wide_op.v

@@ -0,0 +1,34 @@
+
+		module wide_op(
+			a, b, y, c
+		);
+			parameter width = 1024;
+
+			// ADD/SUB: 0/4 + (0 unsigned;unsigned, 1 unsigned;signed, 2 signed;unsigned, 3 signed;signed)
+			parameter op = 0;
+
+			localparam ywidth = width; // (op == MUL) ? width * 2 : width;
+			input[width-1:0] a;
+			input[width-1:0] b;
+			output [width-1:0] y;
+			output c;
+
+			generate
+			if (op == 0)
+				assign {c, y} = a + b;
+			else if (op == 1)
+				assign {c, y} = a + $signed(b);
+			else if (op == 2)
+				assign {c, y} = $signed(a) + b;
+			else if (op == 3)
+				assign {c, y} = $signed(a) + $signed(b);
+			else if (op == 4)
+				assign {c, y} = a - b;
+			else if (op == 5)
+				assign {c, y} = a - $signed(b);
+			else if (op == 6)
+				assign {c, y} = $signed(a) - b;
+			else if (op == 7)
+				assign {c, y} = $signed(a) - $signed(b);
+			endgenerate
+		endmodule