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Edge case tests.

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nella 2026-03-13 12:33:26 +01:00
parent 8d0ecbcdc0
commit b6ea0bb4cc
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tests/csa_tree/csa_tree_equiv.ys Normal file
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# Test bit correctness
read_verilog equiv_narrow.v
hierarchy -top equiv_add3
proc; opt_clean
equiv_opt csa_tree
design -load postopt
select -assert-count 1 t:$fa
select -assert-count 1 t:$add
design -reset
log "equiv_add3: ok"
read_verilog equiv_narrow.v
hierarchy -top equiv_add4
proc; opt_clean
equiv_opt csa_tree
design -load postopt
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
log "equiv_add4: ok"
read_verilog equiv_narrow.v
hierarchy -top equiv_add5
proc; opt_clean
equiv_opt csa_tree
design -load postopt
select -assert-min 2 t:$fa
select -assert-count 1 t:$add
design -reset
log "equiv_add5: ok"
read_verilog equiv_narrow.v
hierarchy -top equiv_add8
proc; opt_clean
equiv_opt csa_tree
design -load postopt
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
log "equiv_add8: ok"
read_verilog equiv_narrow.v
hierarchy -top equiv_signed
proc; opt_clean
equiv_opt csa_tree
design -load postopt
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
log "equiv_signed: ok"
read_verilog equiv_narrow.v
hierarchy -top equiv_mixed_w
proc; opt_clean
equiv_opt csa_tree
design -load postopt
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
log "equiv_mixed_w: ok"
read_verilog equiv_narrow.v
hierarchy -top equiv_repeated
proc; opt_clean
equiv_opt csa_tree
design -load postopt
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
log "equiv_repeated: ok"
read_verilog equiv_narrow.v
hierarchy -top equiv_1bit_wide
proc; opt_clean
equiv_opt csa_tree
design -load postopt
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
log "equiv_1bit_wide: ok"