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docs: restructuring images directory

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see also previous commit
Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.
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Krystine Sherwin 2023-11-14 18:54:16 +13:00
parent dbc38d72cf
commit b6e61c16b1
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docs/source/yosys_internals/formats/rtlil_rep.rst
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@ -23,7 +23,7 @@ pass is reading an auxiliary Verilog file such as a cell library, it might
create an additional ``RTLIL::Design`` object and call the Verilog frontend with
this other object to parse the cell library.
.. figure:: /_images/overview_rtlil.*
.. figure:: /_images/internals/overview_rtlil.*
:class: width-helper
:name: fig:Overview_RTLIL