mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-26 02:25:35 +00:00
Code Activity

docs: restructuring images directory

Browse source 
see also previous commit
Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.
This commit is contained in:
Krystine Sherwin 2023-11-14 18:54:16 +13:00
parent dbc38d72cf
commit b6e61c16b1
No known key found for this signature in database
44 changed files with 131 additions and 237 deletions
Download patch file Download diff file Expand all files Collapse all files

2
docs/source/yosys_internals/flow/verilog_frontend.rst
View file

@ -9,7 +9,7 @@ abstract syntax tree (AST) representation of the input. This AST representation
is then passed to the AST frontend that converts it to RTLIL data, as
illustrated in :numref:`Fig. %s <fig:Verilog_flow>`.
.. figure:: /_images/verilog_flow.*
.. figure:: /_images/internals/verilog_flow.*
:class: width-helper
:name: fig:Verilog_flow