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docs: restructuring images directory
see also previous commit Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.
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44 changed files with 131 additions and 237 deletions
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@ -45,7 +45,7 @@ This script, when executed, will show the design after each of the three
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synthesis commands. We will now look at each of these diagrams and explain what
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is shown.
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.. figure:: /_images/011/example_00.*
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.. figure:: /_images/code_examples/show/example_00.*
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:class: width-helper
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Output of the first :cmd:ref:`show` command in :numref:`example_ys`
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@ -77,7 +77,7 @@ original ``always``-block in the second line. Note how the multiplexer from the
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The :cmd:ref:`proc` command transforms the process from the first diagram into a
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multiplexer and a d-type flip-flop, which brings us to the second diagram:
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.. figure:: /_images/011/example_01.*
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.. figure:: /_images/code_examples/show/example_01.*
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:class: width-helper
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Output of the second :cmd:ref:`show` command in :numref:`example_ys`
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@ -99,7 +99,7 @@ call :cmd:ref:`clean` before calling :cmd:ref:`show`.
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In this script we directly call :cmd:ref:`opt` as the next step, which finally
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leads us to the third diagram:
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.. figure:: /_images/011/example_02.*
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.. figure:: /_images/code_examples/show/example_02.*
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:class: width-helper
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:name: example_out
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@ -126,7 +126,7 @@ native objects. While this provides great advantages when analyzing circuits
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that operate on wide integers, it also introduces some additional complexity
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when the individual bits of of a signal vector are accessed.
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.. figure:: /_images/011/splice.*
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.. figure:: /_images/code_examples/show/splice.*
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:class: width-helper
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:name: splice_dia
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@ -154,7 +154,7 @@ Gate level netlists
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:numref:`first_pitfall` shows two common pitfalls when working with designs
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mapped to a cell library:
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.. figure:: /_images/011/cmos_00.*
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.. figure:: /_images/code_examples/show/cmos_00.*
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:class: width-helper
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:name: first_pitfall
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@ -167,7 +167,7 @@ all ports are drawn on the left side the cells are awkwardly arranged in a large
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column. Secondly the two-bit vector ``y`` requires breakout-boxes for its
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individual bits, resulting in an unnecessary complex diagram.
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.. figure:: /_images/011/cmos_01.*
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.. figure:: /_images/code_examples/show/cmos_01.*
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:class: width-helper
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:name: second_pitfall
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@ -350,10 +350,10 @@ reorganizing a module in Yosys and checking the resulting circuit.
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:caption: ``docs/source/code_examples/scrambler/scrambler.ys``
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:end-before: cd ..
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.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p01.*
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.. figure:: /_images/code_examples/scrambler/scrambler_p01.*
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:class: width-helper
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.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p02.*
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.. figure:: /_images/code_examples/scrambler/scrambler_p02.*
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:class: width-helper
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Analyzing the resulting circuit with :doc:`/cmd/eval`:
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@ -430,7 +430,7 @@ if the circuit under investigation is encapsulated in a separate module.
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Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
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.. figure:: /_images/011/memdemo_00.*
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.. figure:: /_images/code_examples/selections/memdemo_00.*
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:class: width-helper
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``memdemo``
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@ -451,18 +451,18 @@ The ``-name`` option is used to specify the name of the new module and also the
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name of the new cell in the current module. The resulting circuits are shown
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below.
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.. figure:: /_images/011/submod_02.*
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.. figure:: /_images/code_examples/selections/submod_02.*
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:class: width-helper
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``outstage``
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.. figure:: /_images/011/submod_03.*
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.. figure:: /_images/code_examples/selections/submod_03.*
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:class: width-helper
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:name: selstage
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``selstage``
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.. figure:: /_images/011/submod_01.*
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.. figure:: /_images/code_examples/selections/submod_01.*
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:class: width-helper
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``scramble``
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@ -154,7 +154,7 @@ to mark portions of code for analysis.)
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Selecting ``a:sumstuff`` in this module will yield the following circuit
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diagram:
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.. figure:: /_images/011/sumprod_00.*
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.. figure:: /_images/code_examples/selections/sumprod_00.*
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:class: width-helper
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:name: sumprod_00
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@ -171,7 +171,7 @@ be achieved using the ``%x`` action, that broadens the selection, i.e. for each
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selected wire it selects all cells connected to the wire and vice versa. So
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:yoscrypt:`show a:sumstuff %x` yields the diagram shown in :numref:`sumprod_01`:
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.. figure:: /_images/011/sumprod_01.*
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.. figure:: /_images/code_examples/selections/sumprod_01.*
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:class: width-helper
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:name: sumprod_01
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@ -192,22 +192,22 @@ input ports.
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The following sequence of diagrams demonstrates this step-wise expansion:
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.. figure:: /_images/011/sumprod_02.*
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.. figure:: /_images/code_examples/selections/sumprod_02.*
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:class: width-helper
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Output of ``show prod`` on :numref:`sumprod`
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.. figure:: /_images/011/sumprod_03.*
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.. figure:: /_images/code_examples/selections/sumprod_03.*
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:class: width-helper
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Output of ``show prod %ci`` on :numref:`sumprod`
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.. figure:: /_images/011/sumprod_04.*
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.. figure:: /_images/code_examples/selections/sumprod_04.*
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:class: width-helper
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Output of ``show prod %ci %ci`` on :numref:`sumprod`
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.. figure:: /_images/011/sumprod_05.*
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.. figure:: /_images/code_examples/selections/sumprod_05.*
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:class: width-helper
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Output of ``show prod %ci %ci %ci`` on :numref:`sumprod`
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@ -242,7 +242,7 @@ We synthesize the circuit using ``proc; opt; memory; opt`` and change to the
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``memdemo`` module with ``cd memdemo``. If we type :cmd:ref:`show` now we see
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the diagram shown in :numref:`memdemo_00`.
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.. figure:: /_images/011/memdemo_00.*
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.. figure:: /_images/code_examples/selections/memdemo_00.*
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:class: width-helper
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:name: memdemo_00
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@ -287,7 +287,7 @@ Or we could decide to tell the ``%ci`` action to not follow the ``CLK`` input:
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show y %ci2:-[CLK]
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.. figure:: /_images/011/memdemo_01.*
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.. figure:: /_images/code_examples/selections/memdemo_01.*
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:class: width-helper
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:name: memdemo_01
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@ -379,7 +379,7 @@ Example:
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:caption: ``docs/source/code_examples/selections/select.ys``
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:name: select_ys
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.. figure:: /_images/res/PRESENTATION_ExAdv/select.*
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.. figure:: /_images/code_examples/selections/select.*
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:class: width-helper
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Circuit diagram produced by :numref:`select_ys`
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