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docs: restructuring images directory

see also previous commit
Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.
This commit is contained in:
Krystine Sherwin 2023-11-14 18:54:16 +13:00
parent dbc38d72cf
commit b6e61c16b1
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44 changed files with 131 additions and 237 deletions

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@ -45,7 +45,7 @@ This script, when executed, will show the design after each of the three
synthesis commands. We will now look at each of these diagrams and explain what
is shown.
.. figure:: /_images/011/example_00.*
.. figure:: /_images/code_examples/show/example_00.*
:class: width-helper
Output of the first :cmd:ref:`show` command in :numref:`example_ys`
@ -77,7 +77,7 @@ original ``always``-block in the second line. Note how the multiplexer from the
The :cmd:ref:`proc` command transforms the process from the first diagram into a
multiplexer and a d-type flip-flop, which brings us to the second diagram:
.. figure:: /_images/011/example_01.*
.. figure:: /_images/code_examples/show/example_01.*
:class: width-helper
Output of the second :cmd:ref:`show` command in :numref:`example_ys`
@ -99,7 +99,7 @@ call :cmd:ref:`clean` before calling :cmd:ref:`show`.
In this script we directly call :cmd:ref:`opt` as the next step, which finally
leads us to the third diagram:
.. figure:: /_images/011/example_02.*
.. figure:: /_images/code_examples/show/example_02.*
:class: width-helper
:name: example_out
@ -126,7 +126,7 @@ native objects. While this provides great advantages when analyzing circuits
that operate on wide integers, it also introduces some additional complexity
when the individual bits of of a signal vector are accessed.
.. figure:: /_images/011/splice.*
.. figure:: /_images/code_examples/show/splice.*
:class: width-helper
:name: splice_dia
@ -154,7 +154,7 @@ Gate level netlists
:numref:`first_pitfall` shows two common pitfalls when working with designs
mapped to a cell library:
.. figure:: /_images/011/cmos_00.*
.. figure:: /_images/code_examples/show/cmos_00.*
:class: width-helper
:name: first_pitfall
@ -167,7 +167,7 @@ all ports are drawn on the left side the cells are awkwardly arranged in a large
column. Secondly the two-bit vector ``y`` requires breakout-boxes for its
individual bits, resulting in an unnecessary complex diagram.
.. figure:: /_images/011/cmos_01.*
.. figure:: /_images/code_examples/show/cmos_01.*
:class: width-helper
:name: second_pitfall
@ -350,10 +350,10 @@ reorganizing a module in Yosys and checking the resulting circuit.
:caption: ``docs/source/code_examples/scrambler/scrambler.ys``
:end-before: cd ..
.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p01.*
.. figure:: /_images/code_examples/scrambler/scrambler_p01.*
:class: width-helper
.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p02.*
.. figure:: /_images/code_examples/scrambler/scrambler_p02.*
:class: width-helper
Analyzing the resulting circuit with :doc:`/cmd/eval`:
@ -430,7 +430,7 @@ if the circuit under investigation is encapsulated in a separate module.
Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
.. figure:: /_images/011/memdemo_00.*
.. figure:: /_images/code_examples/selections/memdemo_00.*
:class: width-helper
``memdemo``
@ -451,18 +451,18 @@ The ``-name`` option is used to specify the name of the new module and also the
name of the new cell in the current module. The resulting circuits are shown
below.
.. figure:: /_images/011/submod_02.*
.. figure:: /_images/code_examples/selections/submod_02.*
:class: width-helper
``outstage``
.. figure:: /_images/011/submod_03.*
.. figure:: /_images/code_examples/selections/submod_03.*
:class: width-helper
:name: selstage
``selstage``
.. figure:: /_images/011/submod_01.*
.. figure:: /_images/code_examples/selections/submod_01.*
:class: width-helper
``scramble``

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@ -154,7 +154,7 @@ to mark portions of code for analysis.)
Selecting ``a:sumstuff`` in this module will yield the following circuit
diagram:
.. figure:: /_images/011/sumprod_00.*
.. figure:: /_images/code_examples/selections/sumprod_00.*
:class: width-helper
:name: sumprod_00
@ -171,7 +171,7 @@ be achieved using the ``%x`` action, that broadens the selection, i.e. for each
selected wire it selects all cells connected to the wire and vice versa. So
:yoscrypt:`show a:sumstuff %x` yields the diagram shown in :numref:`sumprod_01`:
.. figure:: /_images/011/sumprod_01.*
.. figure:: /_images/code_examples/selections/sumprod_01.*
:class: width-helper
:name: sumprod_01
@ -192,22 +192,22 @@ input ports.
The following sequence of diagrams demonstrates this step-wise expansion:
.. figure:: /_images/011/sumprod_02.*
.. figure:: /_images/code_examples/selections/sumprod_02.*
:class: width-helper
Output of ``show prod`` on :numref:`sumprod`
.. figure:: /_images/011/sumprod_03.*
.. figure:: /_images/code_examples/selections/sumprod_03.*
:class: width-helper
Output of ``show prod %ci`` on :numref:`sumprod`
.. figure:: /_images/011/sumprod_04.*
.. figure:: /_images/code_examples/selections/sumprod_04.*
:class: width-helper
Output of ``show prod %ci %ci`` on :numref:`sumprod`
.. figure:: /_images/011/sumprod_05.*
.. figure:: /_images/code_examples/selections/sumprod_05.*
:class: width-helper
Output of ``show prod %ci %ci %ci`` on :numref:`sumprod`
@ -242,7 +242,7 @@ We synthesize the circuit using ``proc; opt; memory; opt`` and change to the
``memdemo`` module with ``cd memdemo``. If we type :cmd:ref:`show` now we see
the diagram shown in :numref:`memdemo_00`.
.. figure:: /_images/011/memdemo_00.*
.. figure:: /_images/code_examples/selections/memdemo_00.*
:class: width-helper
:name: memdemo_00
@ -287,7 +287,7 @@ Or we could decide to tell the ``%ci`` action to not follow the ``CLK`` input:
show y %ci2:-[CLK]
.. figure:: /_images/011/memdemo_01.*
.. figure:: /_images/code_examples/selections/memdemo_01.*
:class: width-helper
:name: memdemo_01
@ -379,7 +379,7 @@ Example:
:caption: ``docs/source/code_examples/selections/select.ys``
:name: select_ys
.. figure:: /_images/res/PRESENTATION_ExAdv/select.*
.. figure:: /_images/code_examples/selections/select.*
:class: width-helper
Circuit diagram produced by :numref:`select_ys`