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tests/verific: ensure mixed -f requires VHDL unit

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Natalia 2026-01-28 22:46:10 -08:00
parent 5a64fe2d91
commit b6c148f84a
2 changed files with 3 additions and 3 deletions
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3
tests/verific/mixed_flist.sv
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@ -1,3 +1,4 @@
module sv_top(input logic a, output logic y); module sv_top(input logic a, output logic y);
assign y = a; // Instantiates VHDL entity to ensure mixed -f list is required
vhdl_mod u_vhdl(.a(a), .y(y));
endmodule endmodule

3
tests/verific/mixed_flist.ys
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@ -1,4 +1,3 @@
verific -f -sv mixed_flist.flist verific -f -sv mixed_flist.flist
verific -import -all verific -import sv_top
select -assert-mod-count 1 sv_top select -assert-mod-count 1 sv_top
select -assert-mod-count 2 =*