mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Bugfix in "techmap -extern"

Browse source
This commit is contained in:
Clifford Wolf 2014-08-02 20:54:30 +02:00
parent 8e7361f128
commit b6acbc82e6
2 changed files with 17 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

1
passes/techmap/techmap.cc
View file

@ -504,6 +504,7 @@ struct TechmapWorker
RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
wire->port_input = false;
wire->port_id = 0;
for (int i = 0; i < wire->width; i++) {
port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);