mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Fixed off-by-one bug in "hierarchy -check" for positional module args

Browse source
This commit is contained in:
Clifford Wolf 2014-12-24 16:26:18 +01:00
parent e548483c91
commit b6a7e21d2e
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/hierarchy/hierarchy.cc
View file

@ -206,9 +206,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
int id = atoi(conn.first.c_str()+1); int id = atoi(conn.first.c_str()+1);
if (id < 0 || id >= GetSize(mod->ports)) if (id <= 0 || id > GetSize(mod->ports))
log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n", log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n",
log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id + 1); log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id);
} else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0) } else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n", log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first)); log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));