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Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
This commit is contained in:
Eddie Hung
commit
b6a1f627b5
77 changed files with 4480 additions and 1957 deletions
32
tests/arch/ecp5/opt_lut_ins.ys
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32
tests/arch/ecp5/opt_lut_ins.ys
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@ -0,0 +1,32 @@
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read_ilang << EOF
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module \top
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wire input 1 \A
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wire input 2 \B
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wire input 3 \C
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wire input 4 \D
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wire output 5 \Z
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cell \LUT4 $0
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parameter \INIT 16'1111110011000000
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connect \A \A
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connect \B \B
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connect \C \C
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connect \D \D
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connect \Z \Z
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end
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end
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EOF
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read_verilog -lib +/ecp5/cells_sim.v
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equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech ecp5
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design -load postopt
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select -assert-count 1 top/t:LUT4
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select -assert-count 0 top/w:A %co top/t:LUT4 %i
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select -assert-count 1 top/w:B %co top/t:LUT4 %i
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@ -36,6 +36,6 @@ proc
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 11 t:EFX_LUT4
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select -assert-max 12 t:EFX_LUT4
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select -assert-none t:EFX_LUT4 %% t:* %D
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@ -18,13 +18,13 @@ proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 4 t:LUT4
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select -assert-count 4 t:LUT*
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select -assert-count 2 t:MUX2_LUT5
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select -assert-count 1 t:MUX2_LUT6
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select -assert-count 6 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
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select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux8
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@ -35,7 +35,7 @@ cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 11 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
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select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top mux16
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@ -46,4 +46,4 @@ cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 20 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D
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select -assert-none t:GND t:VCC t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D
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72
tests/arch/ice40/bug1597.ys
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72
tests/arch/ice40/bug1597.ys
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@ -0,0 +1,72 @@
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read_verilog <<EOT
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module top (
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input CLK, PIN_1, PIN_2, PIN_3, PIN_4, PIN_5,
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PIN_6, PIN_7, PIN_8, PIN_9, PIN_10, PIN_11, PIN_12, PIN_13, PIN_25,
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output USBPU, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18,
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PIN_19, PIN_20, PIN_21, PIN_22, PIN_23, PIN_24,
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);
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assign USBPU = 0;
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wire[5:0] parOut;
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wire[5:0] chrg;
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assign PIN_14 = parOut[0];
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assign PIN_15 = parOut[1];
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assign PIN_16 = parOut[2];
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assign PIN_17 = parOut[3];
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assign PIN_18 = parOut[4];
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assign PIN_19 = parOut[5];
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assign chrg[0] = PIN_3;
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assign chrg[1] = PIN_4;
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assign chrg[2] = PIN_5;
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assign chrg[3] = PIN_6;
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assign chrg[4] = PIN_7;
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assign chrg[5] = PIN_8;
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SSCounter6o sc6(PIN_1, CLK, PIN_2, PIN_9, chrg, parOut);
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endmodule
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module SSCounter6 (input wire rst, clk, adv, jmp, input wire [5:0] in, output reg[5:0] out);
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always @(posedge clk, posedge rst)
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if (rst) out <= 0;
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else if (adv || jmp) out <= jmp ? in : out + 1;
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endmodule
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// Optimized 6 bit counter, it should takes 7 cells.
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/* b[5:1] /* b[0]
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1010101010101010 in 1010101010101010 in
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1100110011001100 jmp 1100110011001100 jmp
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1111000011110000 loop 1111000011110000 loop
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1111111100000000 carry 1111111100000000 -
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---------------------- ----------------------
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1000101110111000 out 1000101110001011 out
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8 B B 8 8 B 8 B
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*/
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module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output wire[5:0] out);
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wire[4:0] co;
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wire[5:0] lo;
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wire ien;
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SB_LUT4 #(.LUT_INIT(16'hFFF0)) lien (ien, 0, 0, adv, jmp);
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SB_CARRY c0 (co[0], jmp, out[0], 1),
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c1 (co[1], jmp, out[1], co[0]),
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c2 (co[2], jmp, out[2], co[1]),
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c3 (co[3], jmp, out[3], co[2]),
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c4 (co[4], jmp, out[4], co[3]);
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SB_DFFER d0 (out[0], clk, ien, rst, lo[0]),
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d1 (out[1], clk, ien, rst, lo[1]),
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d2 (out[2], clk, ien, rst, lo[2]),
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d3 (out[3], clk, ien, rst, lo[3]),
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d4 (out[4], clk, ien, rst, lo[4]),
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d5 (out[5], clk, ien, rst, lo[5]);
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SB_LUT4 #(.LUT_INIT(16'h8B8B)) l0 (lo[0], in[0], jmp, out[0], 0);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l1 (lo[1], in[1], jmp, out[1], co[0]);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l2 (lo[2], in[2], jmp, out[2], co[1]);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l3 (lo[3], in[3], jmp, out[3], co[2]);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l4 (lo[4], in[4], jmp, out[4], co[3]);
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SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]);
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endmodule
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EOT
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hierarchy -top top
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flatten
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equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40
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@ -1,23 +1,3 @@
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read_verilog -icells -formal <<EOT
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module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
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parameter LUT = 0;
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SB_CARRY carry (
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.I0(A),
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.I1(B),
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.CI(CI),
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.CO(CO)
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);
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\$lut #(
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.WIDTH(4),
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.LUT(LUT)
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) lut (
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.A({I0,A,B,I3}),
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.Y(O)
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);
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endmodule
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EOT
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design -stash unmap
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read_verilog -icells -formal <<EOT
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module top(input CI, I0, output [1:0] CO, output O);
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wire A = 1'b0, B = 1'b0;
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@ -26,13 +6,14 @@ module top(input CI, I0, output [1:0] CO, output O);
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// A[1]: 1100 1100 1100 1100
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// A[2]: 1111 0000 1111 0000
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// A[3]: 1111 1111 0000 0000
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.LUT(~16'b 0110_1001_1001_0110)
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.LUT(~16'b 0110_1001_1001_0110),
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.I3_IS_CI(1'b1)
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) u0 (
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.A(A),
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.B(B),
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.CI(CI),
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.I0(I0),
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.I3(CI),
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.I3(1'bx),
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.CO(CO[0]),
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.O(O)
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);
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@ -40,7 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
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endmodule
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EOT
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equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
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equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
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design -load postopt
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select -assert-count 1 t:*
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select -assert-count 1 t:$lut
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@ -105,3 +86,33 @@ select -assert-count 1 t:SB_LUT4
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select -assert-count 1 t:SB_CARRY
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select -assert-count 1 t:SB_CARRY a:keep %i
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select -assert-count 1 t:SB_CARRY c:carry %i
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design -reset
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read_verilog -icells <<EOT
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module top(input I3, I2, I1, I0, output O, O2);
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SB_LUT4 #(
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.LUT_INIT(8'b 1001_0110)
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) u0 (
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.I0(I0),
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.I1(I1),
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.I2(I2),
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.I3(),
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.O(O)
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);
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wire CO;
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\$__ICE40_CARRY_WRAPPER #(
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.LUT(~8'b 1001_0110),
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.I3_IS_CI(1'b0)
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) u1 (
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.A(1'b0),
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.B(1'b0),
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.CI(1'b0),
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.I0(),
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.I3(),
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.CO(CO),
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.O(O2)
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);
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endmodule
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EOT
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ice40_opt
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25
tests/arch/xilinx/opt_lut_ins.ys
Normal file
25
tests/arch/xilinx/opt_lut_ins.ys
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@ -0,0 +1,25 @@
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read_ilang << EOF
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module \top
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wire width 4 input 1 \A
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wire output 2 \O
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cell \LUT4 $0
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parameter \INIT 16'1111110011000000
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connect \I0 \A [0]
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connect \I1 \A [1]
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connect \I2 \A [2]
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connect \I3 \A [3]
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connect \O \O
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end
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end
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EOF
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equiv_opt -assert -map +/xilinx/cells_sim.v opt_lut_ins -tech xilinx
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design -load postopt
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select -assert-count 1 t:LUT3
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5
tests/arch/xilinx/tribuf.sh
Normal file
5
tests/arch/xilinx/tribuf.sh
Normal file
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@ -0,0 +1,5 @@
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! ../../../yosys ../common/tribuf.v -qp "synth_xilinx"
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../../../yosys ../common/tribuf.v -qp "synth_xilinx -iopad; \
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select -assert-count 2 t:IBUF; \
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select -assert-count 1 t:INV; \
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select -assert-count 1 t:OBUFT"
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