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abc9_ops: ignore inouts of all cell outputs for topo ordering

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This commit is contained in:
Eddie Hung 2020-01-13 23:33:37 -08:00
parent eb7dd7d374
commit b678b15c6d
1 changed files with 6 additions and 2 deletions
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8
passes/techmap/abc9_ops.cc
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@ -488,7 +488,9 @@ void reintegrate(RTLIL::Module *module)
RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
bit_users[a_bit].insert(mapped_cell->name);
bit_drivers[y_bit].insert(mapped_cell->name);
// Ignore inouts for topo ordering
if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output))
bit_drivers[y_bit].insert(mapped_cell->name);
if (!a_bit.wire) {
mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
@ -598,7 +600,9 @@ void reintegrate(RTLIL::Module *module)
for (const auto &i : inputs)
bit_users[i].insert(mapped_cell->name);
for (const auto &i : outputs)
bit_drivers[i].insert(mapped_cell->name);
// Ignore inouts for topo ordering
if (i.wire && !(i.wire->port_input && i.wire->port_output))
bit_drivers[i].insert(mapped_cell->name);
}
int input_count = 0, output_count = 0;