mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 13:29:12 +00:00
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
This commit is contained in:
Eddie Hung
GitHub
commit
b66c99ece0
6 changed files with 291 additions and 14 deletions
|
|
@ -985,7 +985,7 @@ void AigerReader::post_process()
|
|||
// operate (and run checks on) this one module
|
||||
RTLIL::Design *mapped_design = new RTLIL::Design;
|
||||
mapped_design->add(module);
|
||||
Pass::call(mapped_design, "clean -purge");
|
||||
Pass::call(mapped_design, "clean");
|
||||
mapped_design->modules_.erase(module->name);
|
||||
delete mapped_design;
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h))
|
|||
|
||||
PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul.pmg
|
||||
PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
|
||||
PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmux.pmg
|
||||
|
||||
passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
|
||||
$(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^)
|
||||
|
|
|
|||
|
|
@ -60,6 +60,7 @@ struct PeepoptPass : public Pass {
|
|||
peepopt_pm pm(module, module->selected_cells());
|
||||
pm.run_shiftmul();
|
||||
pm.run_muldiv();
|
||||
pm.run_dffmux();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
113
passes/pmgen/peepopt_dffmux.pmg
Normal file
113
passes/pmgen/peepopt_dffmux.pmg
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
pattern dffmux
|
||||
|
||||
state <IdString> cemuxAB rstmuxBA
|
||||
state <SigSpec> sigD
|
||||
|
||||
match dff
|
||||
select dff->type == $dff
|
||||
select GetSize(port(dff, \D)) > 1
|
||||
endmatch
|
||||
|
||||
match rstmux
|
||||
select rstmux->type == $mux
|
||||
select GetSize(port(rstmux, \Y)) > 1
|
||||
index <SigSpec> port(rstmux, \Y) === port(dff, \D)
|
||||
choice <IdString> BA {\B, \A}
|
||||
select port(rstmux, BA).is_fully_const()
|
||||
set rstmuxBA BA
|
||||
optional
|
||||
endmatch
|
||||
|
||||
code sigD
|
||||
if (rstmux)
|
||||
sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
|
||||
else
|
||||
sigD = port(dff, \D);
|
||||
endcode
|
||||
|
||||
match cemux
|
||||
select cemux->type == $mux
|
||||
select GetSize(port(cemux, \Y)) > 1
|
||||
index <SigSpec> port(cemux, \Y) === sigD
|
||||
choice <IdString> AB {\A, \B}
|
||||
index <SigSpec> port(cemux, AB) === port(dff, \Q)
|
||||
set cemuxAB AB
|
||||
endmatch
|
||||
|
||||
code
|
||||
SigSpec D = port(cemux, cemuxAB == \A ? \B : \A);
|
||||
SigSpec Q = port(dff, \Q);
|
||||
Const rst;
|
||||
if (rstmux)
|
||||
rst = port(rstmux, rstmuxBA).as_const();
|
||||
int width = GetSize(D);
|
||||
|
||||
SigSpec &ceA = cemux->connections_.at(\A);
|
||||
SigSpec &ceB = cemux->connections_.at(\B);
|
||||
SigSpec &ceY = cemux->connections_.at(\Y);
|
||||
SigSpec &dffD = dff->connections_.at(\D);
|
||||
SigSpec &dffQ = dff->connections_.at(\Q);
|
||||
|
||||
if (D[width-1] == D[width-2]) {
|
||||
did_something = true;
|
||||
|
||||
SigBit sign = D[width-1];
|
||||
bool is_signed = sign.wire;
|
||||
int i;
|
||||
for (i = width-1; i >= 2; i--) {
|
||||
if (!is_signed) {
|
||||
module->connect(Q[i], sign);
|
||||
if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
|
||||
break;
|
||||
}
|
||||
else {
|
||||
module->connect(Q[i], Q[i-1]);
|
||||
if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ceA.remove(i, width-i);
|
||||
ceB.remove(i, width-i);
|
||||
ceY.remove(i, width-i);
|
||||
cemux->fixup_parameters();
|
||||
dffD.remove(i, width-i);
|
||||
dffQ.remove(i, width-i);
|
||||
dff->fixup_parameters();
|
||||
|
||||
log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
|
||||
accept;
|
||||
}
|
||||
else {
|
||||
int count = 0;
|
||||
for (int i = width-1; i >= 0; i--) {
|
||||
if (D[i].wire)
|
||||
continue;
|
||||
Wire *w = Q[i].wire;
|
||||
auto it = w->attributes.find(\init);
|
||||
State init;
|
||||
if (it != w->attributes.end())
|
||||
init = it->second[Q[i].offset];
|
||||
else
|
||||
init = State::Sx;
|
||||
|
||||
if (init == State::Sx || init == D[i].data) {
|
||||
count++;
|
||||
module->connect(Q[i], D[i]);
|
||||
ceA.remove(i);
|
||||
ceB.remove(i);
|
||||
ceY.remove(i);
|
||||
dffD.remove(i);
|
||||
dffQ.remove(i);
|
||||
}
|
||||
}
|
||||
if (count > 0) {
|
||||
did_something = true;
|
||||
cemux->fixup_parameters();
|
||||
dff->fixup_parameters();
|
||||
log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
|
||||
}
|
||||
|
||||
accept;
|
||||
}
|
||||
endcode
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
|
||||
assign o = i[s*W+:W];
|
||||
endmodule
|
||||
|
||||
module peepopt_shiftmul_1 (output y, input [2:0] w);
|
||||
assign y = 1'b1 >> (w * (3'b110));
|
||||
endmodule
|
||||
|
||||
module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
|
||||
wire [3:0] t;
|
||||
assign t = i * 3;
|
||||
assign o = t / 3;
|
||||
endmodule
|
||||
175
tests/various/peepopt.ys
Normal file
175
tests/various/peepopt.ys
Normal file
|
|
@ -0,0 +1,175 @@
|
|||
read_verilog <<EOT
|
||||
module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
|
||||
assign o = i[s*W+:W];
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
prep -nokeepdc
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
clean
|
||||
select -assert-count 1 t:$shiftx
|
||||
select -assert-count 0 t:$shiftx t:* %D
|
||||
|
||||
####################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
|
||||
assign y = 1'b1 >> (w * (3'b110));
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
prep -nokeepdc
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
clean
|
||||
select -assert-count 1 t:$shr
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 0 t:$shr t:$mul %% t:* %D
|
||||
|
||||
####################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module peepopt_shiftmul_2 (input [11:0] D, input [1:0] S, output [11:0] Y);
|
||||
assign Y = D >> (S*3);
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
prep
|
||||
design -save gold
|
||||
peepopt
|
||||
design -stash gate
|
||||
|
||||
design -import gold -as gold peepopt_shiftmul_2
|
||||
design -import gate -as gate peepopt_shiftmul_2
|
||||
|
||||
miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
|
||||
sat -show-public -enable_undef -prove-asserts miter
|
||||
cd gate
|
||||
select -assert-count 1 t:$shr
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 0 t:$shr t:$mul %% t:* %D
|
||||
|
||||
####################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
|
||||
wire [3:0] t;
|
||||
assign t = i * 3;
|
||||
assign o = t / 3;
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
prep -nokeepdc
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
clean
|
||||
select -assert-count 0 t:*
|
||||
|
||||
####################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
|
||||
always @(posedge clk) if (ce) o <= i;
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
proc
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
clean
|
||||
select -assert-count 1 t:$dff r:WIDTH=2 %i
|
||||
select -assert-count 1 t:$mux r:WIDTH=2 %i
|
||||
select -assert-count 0 t:$dff t:$mux %% t:* %D
|
||||
|
||||
####################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
|
||||
always @(posedge clk) if (ce) o <= i;
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
proc
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
clean
|
||||
select -assert-count 1 t:$dff r:WIDTH=2 %i
|
||||
select -assert-count 1 t:$mux r:WIDTH=2 %i
|
||||
select -assert-count 0 t:$dff t:$mux %% t:* %D
|
||||
|
||||
###################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o);
|
||||
always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
proc
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$dff r:WIDTH=2 %i
|
||||
select -assert-count 1 t:$mux r:WIDTH=2 %i
|
||||
select -assert-count 0 t:$dff t:$mux %% t:* %D
|
||||
|
||||
###################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o);
|
||||
always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
proc
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$dff r:WIDTH=5 %i
|
||||
select -assert-count 1 t:$mux r:WIDTH=5 %i
|
||||
select -assert-count 0 t:$dff t:$mux %% t:* %D
|
||||
|
||||
####################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module peepopt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o);
|
||||
always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i;
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
proc
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
wreduce
|
||||
select -assert-count 1 t:$dff r:WIDTH=2 %i
|
||||
select -assert-count 2 t:$mux
|
||||
select -assert-count 2 t:$mux r:WIDTH=2 %i
|
||||
select -assert-count 0 t:$dff t:$mux %% t:* %D
|
||||
|
||||
####################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module peepopt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
|
||||
always @(posedge clk) begin
|
||||
if (ce) o <= i;
|
||||
if (!rstn) o <= 4'b1111;
|
||||
end
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
proc
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
wreduce
|
||||
select -assert-count 1 t:$dff r:WIDTH=2 %i
|
||||
select -assert-count 2 t:$mux
|
||||
select -assert-count 2 t:$mux r:WIDTH=2 %i
|
||||
select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
|
||||
Loading…
Add table
Add a link
Reference in a new issue