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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 09:13:06 +02:00
parent 44c3472b9f
commit b659082e4a
6 changed files with 15 additions and 13 deletions
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6
tests/efinix/latches.ys
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@ -1,8 +1,8 @@
read_verilog latches.v
design -save read
proc
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix
cd latchp # Constrain all select calls below inside the top module
@ -12,8 +12,8 @@ select -assert-none t:EFX_LUT4 %% t:* %D
design -load read
proc
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix
cd latchn # Constrain all select calls below inside the top module
@ -23,8 +23,8 @@ select -assert-none t:EFX_LUT4 %% t:* %D
design -load read
proc
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix
cd latchsr # Constrain all select calls below inside the top module