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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 09:13:06 +02:00
parent 44c3472b9f
commit b659082e4a
6 changed files with 15 additions and 13 deletions
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8
tests/efinix/adffs.ys
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@ -1,8 +1,8 @@
read_verilog adffs.v
design -save read
proc
hierarchy -top adff
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
@ -13,8 +13,8 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
proc
hierarchy -top adffn
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
@ -25,8 +25,8 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
proc
hierarchy -top dffs
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
@ -38,8 +38,8 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
design -load read
proc
hierarchy -top ndffnr
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module