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hierarchy - proc reorder

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This commit is contained in:
Miodrag Milanovic 2019-10-18 09:13:06 +02:00
parent 44c3472b9f
commit b659082e4a
6 changed files with 15 additions and 13 deletions
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1
tests/efinix/add_sub.ys
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@ -1,5 +1,6 @@
read_verilog add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module