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Renamed $lut ports to follow A-Y naming scheme

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This commit is contained in:
Clifford Wolf 2014-08-15 14:18:40 +02:00
parent f092b50148
commit b64b38eea2
6 changed files with 38 additions and 39 deletions
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36
techlibs/xilinx/cells.v
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@ -10,41 +10,41 @@ module \$_DFF_P_ (D, C, Q);
endmodule
module \$lut (I, O);
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] I;
output O;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin:lut1
LUT1 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]));
LUT1 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]));
end else
if (WIDTH == 2) begin:lut2
LUT2 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]));
LUT2 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin:lut3
LUT3 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]), .I2(I[2]));
LUT3 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin:lut4
LUT4 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]), .I2(I[2]),
.I3(I[3]));
LUT4 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]));
end else
if (WIDTH == 5) begin:lut5
LUT5 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]), .I2(I[2]),
.I3(I[3]), .I4(I[4]));
LUT5 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6) begin:lut6
LUT6 #(.INIT(LUT)) fpga_lut (.O(O),
.I0(I[0]), .I1(I[1]), .I2(I[2]),
.I3(I[3]), .I4(I[4]), .I5(I[5]));
LUT6 #(.INIT(LUT)) fpga_lut (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
end else begin:error
wire _TECHMAP_FAIL_ = 1;
end