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Renamed $lut ports to follow A-Y naming scheme

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This commit is contained in:
Clifford Wolf 2014-08-15 14:18:40 +02:00
parent f092b50148
commit b64b38eea2
6 changed files with 38 additions and 39 deletions
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4
passes/abc/blifparse.cc
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@ -195,8 +195,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->setPort("\\I", input_sig);
cell->setPort("\\O", output_sig);
cell->setPort("\\A", input_sig);
cell->setPort("\\Y", output_sig);
lutptr = &cell->parameters.at("\\LUT");
lut_default_state = RTLIL::State::Sx;
continue;