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fabulous: Allow adding extra custom prims and map rules

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2022-11-16 13:35:37 +01:00 • committed by myrtle
parent f111bbdf40
commit b6467f0801
4 changed files with 53 additions and 0 deletions
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32
techlibs/fabulous/synth_fabulous.cc
View file

@ -65,6 +65,14 @@ struct SynthPass : public ScriptPass
log(" -plib <primitive_library.v>\n"); log(" -plib <primitive_library.v>\n");
log(" use the specified Verilog file as a primitive library.\n"); log(" use the specified Verilog file as a primitive library.\n");
log("\n"); log("\n");
log(" -extra-plib <primitive_library.v>\n");
log(" use the specified Verilog file for extra primitives (can be specified multiple\n");
log(" times).\n");
log("\n");
log(" -extra-map <techamp.v>\n");
log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n");
log(" times).\n");
log("\n");
log(" -encfile <file>\n"); log(" -encfile <file>\n");
log(" passed to 'fsm_recode' via 'fsm'\n"); log(" passed to 'fsm_recode' via 'fsm'\n");
log("\n"); log("\n");
@ -112,6 +120,8 @@ struct SynthPass : public ScriptPass
} }
string top_module, json_file, blif_file, plib, fsm_opts, memory_opts; string top_module, json_file, blif_file, plib, fsm_opts, memory_opts;
std::vector<string> extra_plib, extra_map;
bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten; bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
int lut; int lut;
@ -179,6 +189,14 @@ struct SynthPass : public ScriptPass
plib = args[++argidx]; plib = args[++argidx];
continue; continue;
} }
if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) {
extra_plib.push_back(args[++argidx]);
continue;
}
if (args[argidx] == "-extra-map" && argidx+1 < args.size()) {
extra_map.push_back(args[++argidx]);
continue;
}
if (args[argidx] == "-nofsm") { if (args[argidx] == "-nofsm") {
nofsm = true; nofsm = true;
continue; continue;
@ -237,6 +255,12 @@ struct SynthPass : public ScriptPass
else else
run("read_verilog -lib " + plib); run("read_verilog -lib " + plib);
if (help_mode) {
run("read_verilog -lib <extra_plib.v>", "(for each -extra-plib)");
} else for (auto lib : extra_plib) {
run("read_verilog -lib " + lib);
}
if (check_label("begin")) { if (check_label("begin")) {
if (top_module.empty()) { if (top_module.empty()) {
if (autotop) if (autotop)
@ -325,6 +349,14 @@ struct SynthPass : public ScriptPass
} }
run("techmap -map +/fabulous/latches_map.v"); run("techmap -map +/fabulous/latches_map.v");
run("techmap -map +/fabulous/ff_map.v"); run("techmap -map +/fabulous/ff_map.v");
if (help_mode) {
run("techmap -map <extra_map.v>...", "(for each -extra-map)");
} else if (!extra_map.empty()) {
std::string map_str = "techmap";
for (auto map : extra_map)
map_str += stringf(" -map %s", map.c_str());
run(map_str);
}
run("clean"); run("clean");
} }

3
tests/arch/fabulous/custom_map.v Normal file
View file

@ -0,0 +1,3 @@
module AND(input [7:0] A, B, output [7:0] Y);
ALU #(.MODE("AND")) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
endmodule

8
tests/arch/fabulous/custom_prims.v Normal file
View file

@ -0,0 +1,8 @@
(* blackbox *)
module AND(input [7:0] A, B, output [7:0] Y);
endmodule
(* blackbox *)
module ALU(input [7:0] A, B, output [7:0] Y);
parameter MODE = "";
endmodule

10
tests/arch/fabulous/customisation.ys Normal file
View file

@ -0,0 +1,10 @@
read_verilog <<EOT
module prim_test(input [7:0] a, b, output [7:0] q);
AND and_i (.A(a), .B(b), .Y(q));
endmodule
EOT
# Test adding custom primitives and techmap rules
synth_fabulous -top prim_test -extra-plib custom_prims.v -extra-map custom_map.v
cd prim_test
select -assert-count 1 t:ALU