3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-11 05:30:53 +00:00

fabulous: Allow adding extra custom prims and map rules

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2022-11-16 13:35:37 +01:00 committed by myrtle
parent f111bbdf40
commit b6467f0801
4 changed files with 53 additions and 0 deletions

View file

@ -0,0 +1,3 @@
module AND(input [7:0] A, B, output [7:0] Y);
ALU #(.MODE("AND")) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
endmodule