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Update CHANGELOG and README

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Signed-off-by: David Shah <dave@ds0.me>
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David Shah 2019-11-22 12:46:19 +00:00
parent 49b670ca38
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CHANGELOG
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@ -51,6 +51,8 @@ Yosys 0.9 .. Yosys 0.9-dev
- "synth_ice40 -dsp" to infer DSP blocks
- Added latch support to synth_xilinx
- Added "check -mapped"
- Added checking of SystemVerilog always block types (always_comb,
always_latch and always_ff)
Yosys 0.8 .. Yosys 0.9
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