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added while and repeat support to verilog parser

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Clifford Wolf 2014-06-06 17:40:04 +02:00
parent f9c1cd5edb
commit b5cd7a0179
4 changed files with 31 additions and 1 deletions
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frontends/verilog/lexer.l
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@ -140,6 +140,8 @@ namespace VERILOG_FRONTEND {
"default" { return TOK_DEFAULT; }
"generate" { return TOK_GENERATE; }
"endgenerate" { return TOK_ENDGENERATE; }
"while" { return TOK_WHILE; }
"repeat" { return TOK_REPEAT; }
"assert"([ \t\r\n]+"property")? { return TOK_ASSERT; }