mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Fixed gentb_constant handling in autotest backend

Browse source
This commit is contained in:
Clifford Wolf 2013-12-04 09:09:42 +01:00
parent bb20aceeb3
commit b5afd75b0a
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/autotest/autotest.cc
View file

@ -124,11 +124,11 @@ static void autotest(FILE *f, RTLIL::Design *design)
is_clksignal = true;
}
}
if (is_clksignal && !wire->get_bool_attribute("\\gentb_constant")) {
if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
} else {
signal_in[idy("sig", mod->name, wire->name)] = wire->width;
if (wire->get_bool_attribute("\\gentb_constant"))
if (wire->attributes.count("\\gentb_constant") != 0)
signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string();
}
fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());