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Added support for non-standard "module mod_name(...);" syntax

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This commit is contained in:
Clifford Wolf 2014-08-04 15:19:24 +02:00
parent ebbbe7fc83
commit b5a3419ac2
2 changed files with 12 additions and 1 deletions
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5
README
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@ -276,6 +276,11 @@ Verilog Attributes and non-standard features
for everything that comes after the {* ... *} statement. (Reset
by adding an empty {* *} statement.)
- Modules can be declared with "module mod_name(...);" (with three dots
instead of a list of moudle ports). With this syntax it is sufficient
to simply declare a module port as 'input' or 'output' in the module
body.
- Sized constants (the syntax <size>'s?[bodh]<value>) support constant
expressions as <size>. If the expresion is not a simple identifier, it
must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010

8
frontends/verilog/parser.y
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@ -55,6 +55,7 @@ namespace VERILOG_FRONTEND {
struct AstNode *current_ast, *current_ast_mod;
int current_function_or_task_port_id;
std::vector<char> case_type_stack;
bool do_not_require_port_stubs;
bool default_nettype_wire;
bool sv_mode;
}
@ -210,6 +211,7 @@ hierarchical_id:
module:
attr TOK_MODULE TOK_ID {
do_not_require_port_stubs = false;
AstNode *mod = new AstNode(AST_MODULE);
current_ast->children.push_back(mod);
current_ast_mod = mod;
@ -244,7 +246,8 @@ single_module_para:
};
module_args_opt:
'(' ')' | /* empty */ | '(' module_args optional_comma ')';
'(' ')' | /* empty */ | '(' module_args optional_comma ')' |
'(' '.' '.' '.' ')' { do_not_require_port_stubs = true; };
module_args:
module_arg | module_args ',' module_arg;
@ -582,6 +585,9 @@ wire_name:
node->children.push_back($2);
}
if (current_function_or_task == NULL) {
if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
port_stubs[*$1] = ++port_counter;
}
if (port_stubs.count(*$1) != 0) {
if (!node->is_input && !node->is_output)
frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());