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Merge pull request #1718 from boqwxp/precise_locations

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Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
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Claire Wolf 2020-03-03 08:38:32 -08:00 • committed by GitHub
commit b597f85b13
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11 changed files with 388 additions and 305 deletions
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4
tests/various/mem2reg.ys
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@ -9,6 +9,6 @@ EOT
proc
cd top
select -assert-count 1 m:data1 a:src=<<EOT:4 %i
select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i
select -assert-count 1 m:data1 a:src=<<EOT:4.43-4.48 %i
select -assert-count 2 w:data2[*] a:src=<<EOT:5.41-5.46 %i
select -assert-none a:mem2reg