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chore: fix master branch refs

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Signed-off-by: Rui Chen <rui@chenrui.dev>
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Rui Chen 2024-03-24 00:41:40 -04:00
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4
docs/source/using_yosys/more_scripting/interactive_investigation.rst
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@ -18,7 +18,7 @@ in the circuit diagrams generated by it. The code used is included in the Yosys
code base under |code_examples/show|_.
.. |code_examples/show| replace:: :file:`docs/source/code_examples/show`
.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/show
.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/show
A simple circuit
^^^^^^^^^^^^^^^^
@ -337,7 +337,7 @@ The code used is included in the Yosys code base under
|code_examples/scrambler|_.
.. |code_examples/scrambler| replace:: :file:`docs/source/code_examples/scrambler`
.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/scrambler
.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/scrambler
Changing design hierarchy
^^^^^^^^^^^^^^^^^^^^^^^^^

4
docs/source/using_yosys/more_scripting/model_checking.rst
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@ -29,7 +29,7 @@ Let's take a look at an example included in the Yosys code base under
|code_examples/synth_flow|_:
.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
.. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
:language: verilog
@ -81,7 +81,7 @@ The code used in this section is included in the Yosys code base under
|code_examples/axis|_.
.. |code_examples/axis| replace:: :file:`docs/source/code_examples/axis`
.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/axis
.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/axis
The following AXI4 Stream Master has a bug. But the bug is not exposed if the
slave keeps ``tready`` asserted all the time. (Something a test bench might do.)

2
docs/source/using_yosys/more_scripting/selections.rst
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@ -405,7 +405,7 @@ those cases selection variables must be used to capture more complex selections.
Example code from |code_examples/selections|_:
.. |code_examples/selections| replace:: :file:`docs/source/code_examples/selections`
.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/selections
.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/selections
.. literalinclude:: /code_examples/selections/select.v
:language: verilog