mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	Added support for verilog === operator
This commit is contained in:
		
							parent
							
								
									595db0d7b9
								
							
						
					
					
						commit
						b56e06d2f5
					
				
					 1 changed files with 2 additions and 0 deletions
				
			
		|  | @ -233,6 +233,8 @@ supply1 { return TOK_SUPPLY1; } | ||||||
| "<=" { return OP_LE; } | "<=" { return OP_LE; } | ||||||
| ">=" { return OP_GE; } | ">=" { return OP_GE; } | ||||||
| 
 | 
 | ||||||
|  | "===" { return OP_EQ; } | ||||||
|  | 
 | ||||||
|  /* "~&" { return OP_NAND; } */ |  /* "~&" { return OP_NAND; } */ | ||||||
|  /* "~|" { return OP_NOR;  } */ |  /* "~|" { return OP_NOR;  } */ | ||||||
| "~^" { return OP_XNOR; } | "~^" { return OP_XNOR; } | ||||||
|  |  | ||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue