mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Set past_d value for init state

Browse source
This commit is contained in:
Miodrag Milanovic 2022-04-02 10:33:41 +02:00
parent 8ca9737180
commit b54aecd80a
1 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/sat/sim.cc
View file

@ -782,6 +782,7 @@ struct SimInstance
{ {
for (auto &it : ff_database) for (auto &it : ff_database)
{ {
ff_state_t &ff = it.second;
SigSpec qsig = it.second.data.sig_q; SigSpec qsig = it.second.data.sig_q;
if (qsig.is_wire()) { if (qsig.is_wire()) {
IdString name = qsig.as_wire()->name; IdString name = qsig.as_wire()->name;
@ -790,6 +791,7 @@ struct SimInstance
log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str()); log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
if (id!=0) { if (id!=0) {
Const fst_val = Const::from_string(shared->fst->valueOf(id)); Const fst_val = Const::from_string(shared->fst->valueOf(id));
ff.past_d = fst_val;
set_state(qsig, fst_val); set_state(qsig, fst_val);
} }
} }