From b545fc4728f6b69216be09a4bfd8e902de5d61c7 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Wed, 15 Jan 2025 02:20:03 -0800 Subject: [PATCH] Reduce submod verbosity --- passes/hierarchy/submod.cc | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index f1541d65d..a23a84a9f 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -88,6 +88,7 @@ struct SubmodWorker void handle_submodule(SubModule &submod) { log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str()); + log_flush(); wire_flags.clear(); for (RTLIL::Cell *cell : submod.cells) { @@ -192,13 +193,13 @@ struct SubmodWorker } if (new_wire->port_input && new_wire->port_output) - log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str()); + log_debug(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str()); else if (new_wire->port_input) - log(" signal %s: input %s\n", wire->name.c_str(), new_wire->name.c_str()); + log_debug(" signal %s: input %s\n", wire->name.c_str(), new_wire->name.c_str()); else if (new_wire->port_output) - log(" signal %s: output %s\n", wire->name.c_str(), new_wire->name.c_str()); + log_debug(" signal %s: output %s\n", wire->name.c_str(), new_wire->name.c_str()); else - log(" signal %s: internal\n", wire->name.c_str()); + log_debug(" signal %s: internal\n", wire->name.c_str()); flags.new_wire = new_wire; } @@ -214,7 +215,7 @@ struct SubmodWorker log_assert(wire_flags.count(bit.wire) > 0); bit.wire = wire_flags.at(bit.wire).new_wire; } - log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); + log_debug(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); if (!copy_mode) module->remove(cell); }